hi everyone in this video you are going to learn about gate logical gate logic in the previous video we have seen switch logic these two are used to construct a different logic functions like gatings or any type of logic now this video completely explains about what are the basic gate logic functions available with nmos and CMOS logic circuitry so if you see the gate logic in the first one we have the inverter inverter may be nmos inverter or it may be a CMOS inverter or it may be a bi CMOS inverter also okay in the complementary metal oxide semiconductor technology the first and the basic circuit was inverter because the circuit itself produces a complemented outfolder okay you are not intentionally generating but the circuit Behavior itself is generating a complemented version of the inputs okay and along with this inverter the same circuit can also be extended in the gate logic to create nand Gates to create nand Gates and the same can also be extended with the creation of nor gate if you see here I am going to explain about the complemented versions of the basic Gates nand gate and nor gate and or Gator so this neander nor as these land nor gates are Universal Gates and the most important Gates that are generated basically by giving the inputs is a complemented version of the CMOS that's why we are going to discuss here navigate and nor Gates of course once Navigator not designed the negate and or gate are different logic functions can be easily determined using this Nandan nor Gates here nand Gates and organs are also designed using nmos transistor Prima CMOS logic and as well as biceps logically and here also nor gates are designed with these three combinations so nmos logic what do you mean by nmos Logic and mouse logic If You observe nmos logic consisting of all nmos transistors all nmos transistors that means this logic function the logic circuitry which is an almost logic Finance circuitry which does not include any other type of transistors pmas are any type so all inverse transistors are needed here the nmos may be a depletion mode transistor or enhancement mode transistor depending upon the requirement and in CMOS logic circuit the name clearly tells that it is a complementary metal oxide semiconductor which consisting of consists of P Mass transistor and as well as e n must transistor It's a combination of complementary matlocks or semiconductor is a combination of both pmas and as well as nmos whereas pmos transistors are connected in the pull up place and nmos transistors are connected in the pull down place okay and coming to the by CMOS logical what do you mean by bison is nothing but a combination of bipolar technology plus CMOS technology combination of bipolar technology and CMOS technology it is equivalent to bipolar technology that may be either npn or PNP transistors plus this is CMOS technology is having again pmos transistors and as well as nmos transistors so overall we can say It's a combination of obesity and PN transistor or BJT PNP transistor plus pmos transistor and nmos transistor cell okay so in this way using all these these different methods you are going to create this three logic circuitry one is inverter another one is nand gate and the other one is nor Gator okay let us see one by one how the circuits are going to be realized so the first one is inverter so see the first figure circuit a shows the nmos inverter where it consists of two nmos transistors one is in the depletion mode this is the depletion mode transistor and it is the enhancement mode transistor the depletion mode transistor we are taking with the channel depletion mode transistor we are taking with the channel and the input of this we know the depletion number transistor we no need to switch on this transistor because initially it is having by default it is having a channel from source to range so that the input is not required and it is folded back towards the drain terminal okay if you if you say this is the right terminal this is the trend terminal and this is a source terminal so the input is folded back towards the gate drain terminal to make a high high influence device okay nothing but it simply acts as on transistor okay we need a we are on transition but we need we need a on Resistance from this vdd up to this output terminal okay so that resistance is made up of only a on transistor which is nothing but a depletion or transistor why we are taking the depletion mode transistor means it is giving High a good logic function okay when input is equal to 0 the transistor the bottom transistor is set to be in off State then there is a current flow from vdd to the output in that situation the maximum logical level can be obtained when we are having a depletion mode transistor here that is the reason why we are taking a depletion mode transistor we are getting 100 percent 5 volts here okay now coming to this CMOS complementary metal oxide semiconductor logic function CMOS logic function is having a pmas transistor in the pull up a place and then must transistor in the pull down place with a common input for these two common input is given to both the transistors pmas and as well as nmos and output is taken at the center of these two the same you see here what is the difference between the first figure and second figure this one and this one both are CMOS logic functions but here in the first figure if you see there is a fourth terminal this is the first terminal second terminal third terminal and this one is the fourth element this fourth terminal is not shown in the in this figure generally it is always there with respect to the mass transistor this fourth terminal shows the substrate terminal both terminal shows the substrate terminal substrate terminal is always connected to the source sir State terminal is always connected to the source okay until and unless we require a biasing supply nothing but suppose if you want to change the threshold voltage VT then body bias effect is needed in that body bias effect definitely we should give some built-in potential between source and substrator okay except that remaining all cases we will generally so short circuit the source and substrate this is the substrate terminal hope you understand substrate terminal is used to change the threshold voltage of the transistor BJT we cannot change the threshold voltage in Mass technology we can change the threshold voltage variable threshold voltage is there in the mass technology another advantage of the mass now coming to this third one which is a bipolar and CMOS technology so we by CMOS technology see Here If You observe that circuit consisting of both the transistors the first one is it is a pmos transistor and this is the nmos transistor and this one is an npn transistor it is also npn transistor okay so these two npn configurations are connected in a push pull configuration where one transistor is in on State and other is in off State and vice versa so these two are said to be in we can say a push pull configuration Wishful configuration okay so suppose if you take a logic 0 function this makes the pmos transistor on and must offer as this transistor is in off State this npn also in off State and as it is in on state there is a current flow directly to the input of this transistor so this transistor is non State and again output will be having a current flow so outputting is equal to logical so in this way the inverters are going to be constructed using this different logic functions like nmos CMOS and by CMOS if you see the logic symbols logic symbol of course it appears same it is having normal uh buffer followed by Bubble nothing but inverter case now coming to this two input nmask CMOS by CMOS nand Gates nand realization is nothing but if you say the output Y is equal to a b bar transistor should be in parallel this is the realization with respect to CMS I told you already triple P we must transistors should be connected in parallel for product realization okay but this case is applicable triple PE case is applicable only with respect to the CMOS logic but if you see the nmos logic nmos logic does not have any problem with respect to the Fuller transistor because in nmos in N Mass pull up is always pull up is always a depletion mode transistor a depletion mode device hope you understand okay in pull up in pull up we are always using a depletion mode transistor for the nmos realization whatever the realization is under and not whatever the realization in pull up we are using a depletion mode transistor and in pull down we are having a and b as they are in series it simply realizes a into B and it is complemented by default coming from the most technology and coming to the CMOS technology CMOS transistor device CMOS is nothing but consisting of pmas and as well as nmos pmas transistors in parallel and nmos transistors are in series if you see the first two circuits the nmos realization from ground to Output here from ground to Output that is common but additionally we are having in place of depletion transistor we are having enhancement mode pmos transistors here okay and coming to the buy CMOS technology again the same SEMA circuitry is extended with the bipolar technology to get the landlogic and the same can be created with the nor logic functions nor is nothing but Y is equal to a plus b bar a plus b bar so a plus b bar is a into B nothing but pmos transistors in product but yes it is blessed so P much transistor should be in series opposite realization with the case of nand gate and coming to this inverse logic nmos is having a depletion or transistor in the pull up but here the A and B are parallel this is CMOS and this one the same CMOS logic is extended with the bipolar technology to get the by C Mass realization in this way we can create the standard and uh what is that Universal Gates using this nmos CMOS and by CMOS Technologies in the next video I will explain what are the different other forms of CMOS logic functions like the pseudo and mass logic and dynamic logic nominologic and clocked CMOS logical thank you