Pipelined RISC-V Architecture

Introduction

• Presenter: Nick
• Series: Bits of Architecture
• Topic: Pipelined RISC-V architecture

What is Pipelining?

• Pipelining: Process of breaking up instruction execution into individual stages.
• Unlike single cycle processors, multi-cycle processors perform one stage of instruction per cycle.
• Allows overlap of instruction execution stages, improving hardware utilization and performance.
  • Eg: One instruction in write-back, another in memory access, another in ALU execute, etc.

Implementation of a Pipelined Processor

• High-Level Architecture: Similar to single cycle implementation but with pipeline registers dividing stages:
  • Instruction Fetch
  • Decode
  • Execute
  • Memory Access
  • Write-Back
• Pipeline Registers: Important for checkpointing state of instructions as they progress through stages.

Need for Pipeline Registers

• Single Cycle Access: In single cycle, an instruction accesses all hardware resources in one cycle.
• Multi-Cycle Limitation: In multi-cycle, each instruction works in one stage per cycle.
• State Checkpointing: Values read out from registers in decode stage are saved in pipeline registers to use in subsequent stages (eg. execute stage).
• Helps maintain different instructions’ states at different stages simultaneously.

Control Signals

• Control Lines: Continue to control the hardware units similarly.
• Control Signals in Pipeline: Must checkpoint control signals as well.
  • Each instruction has specific control signals (eg. load/store vs. r-type instruction).
  • Control Unit: Takes instruction/op-code and generates control signals; saved in pipeline registers.
• Stages with Control Signals:
  • Execute Stage: Two control signals - ALU source, ALU operation.
  • Memory Stage: Three control signals - mem_read, mem_write, branch.
  • Write-Back Stage: Two control signals - mem_to_reg, register_write.

Example Diagram

• Diagram Explanation:
  • Instruction Fetch: Fetch instruction and read registers.
  • Decode: Decode instruction and set control signals, save in pipeline registers.
  • Execute: Use control signals for ALU operations, read values from pipeline registers.
  • Memory: Use control signals for memory operations (read/write).
  • Write-Back: Use control signals for writing back to registers.

Key Points

• Similarity to Single Cycle: Many structures remain the same (multiplexers, program counters, memory, registers, ALUs).
• Pipeline Registers: Added to checkpoint state as instructions pass through stages.

Future Topics

• Forwarding & Bypassing: Detailed discussion in forthcoming videos.

Conclusion

• Presenter: Nick
• Sign-off: Hope you have a nice day!