Fundamental Principles of DRAM

Jul 4, 2024

Fundamental Principles of DRAM

DRAM Memory Cell

  • Basic Unit: Capable of storing a single binary digit (0 or 1).
  • Components:
    • Transistor: Acts as a switch with gate, source, and drain.
    • Capacitor: Stores electric charge; connected to the transistor's drain and to ground.
    • Ground: Reference voltage; often considered as 0 volts.

Transistor Operation

  • Voltage at Source: Blocks current flow.
  • Applied Voltage at Gate: Allows current to flow from source to drain.
  • Closed Gate: Blocks current flow; capacitor remains charged if previously charged.
  • Pass Transistor: Refers to transistor in a memory cell that manages charge/discharge of capacitor.

Charging and Discharging

  • Charge State: Represents a binary 1.
    • Gate open → Current charges capacitor in nanoseconds.
    • Gate closed → Capacitor stays charged.
  • Discharge State: Represents a binary 0.
    • Gate open (source voltage absent) → Capacitor discharges.

Array Organization

  • 2D Arrangement: DRAM cells connected via word lines and bit lines.
  • Sense Amplifiers:
    • Connected to bit lines; detects voltage differences to read cells.
    • Divides DRAM array into sections (Open Bit Line Layout).
    • Uses differential sensing by comparing bit line voltages.

Reading Process

  • Row Precharging: Bit lines precharged to half of DRAM supply voltage (e.g., 1.5V if supply is 3V).
  • Reading a Cell:
    • Word line asserted → Pass transistors open.
    • Charged capacitor discharges slightly; changes bit line voltage by a small amount.
    • Sense amplifiers detect these changes and latch values.
  • Destructive Read: Cells partially discharge, requiring rewrites immediately after reading.
  • Write Back: Sense amplifiers restore original cell values by adjusting bit line voltages.

Refreshing Cells

  • Charge Leakage: Cells naturally leak charge over time.
  • Periodic Refresh: Every cell read/re-written approximately every 64 nanoseconds.

Summary

  • DRAM Cell: Consists of a transistor and capacitor, storing a single binary digit.
  • Arrangement: Cells in a rectangular array, connected by word lines and bit lines.
  • Destructive Read and Refresh: Every read operation is destructive, requiring immediate rewrites; periodic refresh due to charge leakage.