this is the axi specification uh nearly see here how many pages are there 328 but this 328 Pages not complete about axi it is about AC also after axi AC pages will start okay uh today we will discuss uh the port directions suppose whatever the right address signals write data write response read data and response and read address signals there okay so which one is the input which one is the output so like that we have to discuss now but before going to that I will give you some more information in the form of diagrams so this specification you can download from the Google or I sent you already I also got it from Google okay this uh signal meanings uh I already explained in the APB protocol same meanings applicable Here Also I suggest first after are watching APB protocol specification lectures if you watch this one axi you can understand more better so we are discussing about barest and multi- data transfers data transfers transaction different terminologies we are using now so with this uh diagrams help I will explain so that you can understand more better this is Master interface this is slave interface okay this is uh read address Channel with respect to read I am telling with respect to read transaction okay so this is the read address Channel this is the read data and response Channel okay so when Master want to get some data from the slave it will send some address from where it it want the data okay so that's why this address is this direction now then slave will send that data okay I told that data may contain one data transfer or multi- data transfers see here data transfer one data transfer 2 3 4 there are multi- data transfers if there are multi- data transfers like this then it is called a burth to data transfer suppose here only one is there data transfer only one box let us assume then then it won't become a burst data transfer okay so this uh read data and response both directions will be from slave to master okay now this we can consider as a read transaction so this is transfer this one box is transfer for example read transfer or read data transfer together all boxes read burst data read burst data now together this all whatever the operation this is called read operation or we can also call read transaction okay right and one more thing you have to observe here along with address it is sending some control information also we'll discuss about that also very detailed in further lectures now coming to the right transaction or right operation there will be three channels now so now this is the right address channel so Master sending that uh address to the SLP with address it will send control information information also okay so now slave will send the data uh Master will send the data because Master only want to send the data now during right operation so Master is sending the data so that direction is from this to this master to this one here also you may send one data transfer or multi so here there are multi so it is also called burst data transfer previous burst is read data related to read now this is related to write then response response will give by slave here now this direction is from this side okay suppose here why we need response actually Master want to send the data into particular address it informed the address and it send the address when slave is ready but after slave uh get get the AL data got the data it has to inform to the master S I received whatever you sent that's why here response uh needed and now here response is coming from this so This Here Also response Direction same here also response Direction same but why here we need response okay whatever the data sending by the slave to the Master Slave will inform after sending all the the data slay will inform I sent all the data whatever the data you want I sent all the data okay now like that it will send the response I sent after sending it will send the response that response is indicating I sent all the transfers after sending all the transfers only it will send the response okay I hope from this diagram you you understood the meaning of single data transfer whether it is a right or read and barus to data transfer whether it is a right or read and transaction this whole WR operation is Right transaction read operation is read transaction like that or we can also say this all data transfers when suppose when I sending this all datas from this slave to master after sending all datas we can say transaction is completed okay now I will show you uh two more diagrams one more diagram see here this is multimaster multi slave architecture okay so we need interconnect we need inter interconnect this AXA specification giving meaning there are three kind of meanings it is giving for the interface for the meaning of interface AI specification giving three meanings for example a interface can exist between master and the interconnect so this is the master and this is the interconnect between master and interconnect between master and interconnect whatever line is there this line we can call interface this is one meaning there can be second meaning between slave and the interconnect now this is the slave and this is the interconnect between these two also whatever exist at this line this is also called interface this is also interface this is also interface now third meaning between master and slave suppose let us assume there is only one master let us assume I will draw here yeah let us assume there is only one master single Master single slave they will be directly connected there is no need of interconnect in this case this will become the interface a interface can exist between directly Master Slave or between master and interconnect or in between slave and interconnect okay now these all meanings applicable to interface okay now this interface axi Advanced extensible interface this interface is nothing but axi for example axi if we assume all interconnects are all interface Es are axi in that sense these are all our axi interfaces okay now coming to the uh Port directions which one is the input which one is the output because when we want to do code we need to know the port directions okay coming to the right address see here this is the ID channel aw ID so here they are giving source is the master it means what is the meaning of this one what is the meaning of the source I will tell let us assume uh let us assume single Master single slave system there is a master there is a slave they connected each other this is the interface so here when we're doing right address operation right address what is the direction of right address this direction Master to SLP okay so it means this this is one channel we are calling it as aw in this there are multiple signals in this there are multiple signals in the signals one of the signal the First Signal can be aw ID okay this aw ID actually going from Master to slave only so then who is generating this aw ID signal Master is generating now this master will become the source so here this Source indicating which one generating the signal that will become the source okay for example this is master master master all signals source is Master Only If You observe one one this one last one ready slave is the source it means what is a meaning here now this is the master this is the slave so now this ready signal is going from slave to master so who generating this ready slave now this will become the source now this will become the source okay so here whatever the source meaning they given that is applicable to who generating this signal that is the meaning if they given master master generating this signal suppose here Master this signal is generating by Master here if they given slave for example this signal is generating by slave that is the meaning whoever generating that will become the source okay so now but in terms of input and output how to how to know which one is the input which one is the output that I will show now uh for example here only I will show so now whatever the signals generating by Master they will become the inputs input ports whatever the signals generating by by slave they will become the output ports okay now simply remember whatever the signals generating by Master they will become input generating by slave they will become output ports in the code okay I will tell you another meaning of source also here whatever the source meaning I told this is the meaning of here this meaning who generating but I will give you another meaning for source and destination in this case this is the source this is the destination in this case this is the source this is the destination okay now coming to the right to data so master master master only ready we can easily remember okay even in right data in right address only ready become the output now coming to the right response here also ready uh no no here reverse see because that response direction is from slave to master now okay so reverse these all will become slave these this will become master so it means these all will become outputs this will be become the input okay so in this case ready signal is generating by Master Okay in previous cases ready signal is generating by slave but now ready signal is generating by Master okay now I will show you the directions of valid and ready for three uh channels of right transaction for example let us take right address Master Slave this is happening in this way let us take uh write data W this is the direction let us take right response the direction will be like this okay so now here when Master want to send the data first valid will asserted now so that valid direction will be now I will show you valid and ready directions okay this one so this is valid Direction and this will be the righty Direction it requested then it responded Yes I am uh uh ready to take your address like that it requested it responded okay I'm ready to take your data so now M here Master requested okay uh slave is ready it taken data now after taking data complete data transfers slave has to give the response now this response yes I am ready now this response yes I taken all your data okay so now who who want to give the response who has to give the response slave who is waiting for the response master so Master is waiting okay so now valid direction will be like this ready direction will be like this so that's why this is uh not R actually this is B now okay this is B not R this is B so with respect to B B so now valid will be like this ready will be like this okay see now here with respect to valid and ready whoever generating valid they will become source whoever generating ready they will become destination okay now remember this point so here with respect to valid and ready this is the source this is the destination this is the source this is the destination with respect to valid and ready this is the source this is the destination so this two points applicable to every channel whoever generating valid it will become Source ready it will become destination okay now now coming to this signal a here also master master master last one is the SLP here both signals are together uh these all are slaves this one only Master we can simply remember which one is input output now here valid and ready directions we'll see now here also so right read address is going this side this this is Master this is slave master slave read data and response going this side we know these directions now valid Direction ready Direction valid Direction ready Direction okay now these you have to carefully remember here also whoever generating uh this valid it will become Source it will become destination now it will become Source it will become destination okay so we understood input and output directions for the all channels and signals now we'll go to handshake conditions handshake can happen in three ways I will show you three possibilities you know suppose handshake signals are valid and ready valid May asset first ready May asset later or ready May Asser first valid May Asser later or they both may Asser at a time okay they both may assert at a time or one after other in the one after other first valid may start or first asset may start so in three possibilities handshake will happen that three possibilities I will show okay so this is the first possibility handshake one possibility 1 so here this is the so this a in the AI protocol all operations will work with respect to postive clock okay and negative reset and we know for the each signal what is the prefix but for clock and do reset the prefix is a remember clock will be a CL and reset will be a reset it is negative reset so a reset n in the suffix there will be n at the ending small letter okay all right so clock is one clock is 2 3 4 5 so now here information this this information can be address and control information data information response information anything can be all together we can call it as a information okay so now here valid and ready now what about this clock cycle simple whatever the clock they showing here here they telling number so this is not a different thing so this is clock one this is clock h 2 this is clock H three this is clock four like that they indicating that is a meaning okay so now here for example which one is asserted first here asserted means Suppose there is act to high signals and act to low signals assert meaning will be different for both signals suppose for active High signals assert means one when it is going to one it is asserted when it is going to zero it is deasserted with respect to active High signals suppose for active low signals when it is going to high deasserted when it is going to down asserted for example let us take a reset signal reset and clock signal here Suppose there is a clock signal I told here we are taking positive when it is going high we can say asserted when it is going down we can say deasserted suppose let us take reset and I told here we are using negative reset whenever it is going high we can say deasserted whenever it is going down we can say asserted so assert meaning will be different for active high and active low signals okay so here this is with respect to positive this this notation will be applicable so here asserting okay asserting means it is going to high whenever it is asserting at the same time information also will start so until this point this data is not a valid data this is invalid data okay so from this point wherever it asserted from from there valid data started okay now to take the completion of this valid data handshake should happen so now whenever it asserted until taking that valid data handshake complete it will continue as high only it will continue as high only okay now here you can see ready is asserted here ready is asserted but when at this point it is not exactly asserting at clock H so even it is assed here we have to look for the clock we have to look for the clock okay so now here you can see there is a clock AG occurrence and at this point we can see clock AG occurred for valid also so both are asserted both are asserted at positive clock AG so here handshake will complete so this is the point of where handshake is completed data is taken so now no more data so for example there is only one data transfer this is not a birth type if there are multiple transfers uh it will be indicated in another way we will tell with w l signal but ultimately from this uh diagram what we have to understood okay what we have to what we have to understand in this handshake here handshake completed in this handshake just a minute in this handshake valid asserted first then ready this is one category even though it asserted first handshake completed now we'll see second possibility here in the second possibility where handshake is completing here hand shaking is completing both are high at the particular clock H but now in this possibility ready asserted first then valid asserted but here also in this way also handshake will be successful this is second possibility now third possibility see here this is the point where handshake is completing both are asserted at same time so the point is handshake can happen in three different ways both may Asser at a time or anyone can Asser at first valid can asset or ready can asset okay right so this is about today class if you have any doubts you can ask me