Lecture Notes: Designing a Logic Circuit for Binary Division

Introduction

• Topic: Logic circuit design for binary division
• Previous video: Binary division overview
• Current focus: Design a combinational circuit for binary division

Binary Division Overview

• Binary division: Repetitive subtraction
• Steps:
  1. Compare divisor with selected bits of dividend
  2. If divisor < selected bits:
     • Subtract divisor
     • Write 1 in the quotient
     • Append next bit of dividend
     • Right shift divisor
  3. If divisor ≥ selected bits:
     • Do not subtract
     • Write 0 in the quotient
     • Append next bit of dividend
     • Right shift divisor

Basic Operations Involved

• Three operations:
  • Compare
  • Shift
  • Subtraction
• Combining compare and subtract:
  • If subtraction result is positive, output no borrow.
  • If subtraction result is negative, output borrow.

Using Subtractor Circuit

• Block diagram of a 4-bit subtractor shown.
• From borrow output, determine quotient bits:
  • No borrow: quotient bit = 1
  • Borrow: quotient bit = 0
• Need a control circuit for restoration if subtraction is invalid.

Subtraction with Full Adders

• Subtraction using 2's complement:
  • For 4-bit subtraction, invert one number and add 1.
  • Example: 12 - 7 = 12 + (2's complement of 7)
• Carry bit used as quotient bit.

Implementation of Restoration Circuit

• Multiplexer used to restore original number if subtraction is negative.
• Each full adder paired with a 2-to-1 multiplexer.
• Selection input based on carry output of the last full adder.

Shift Operation

• Performed by arranging processing units in the combinational circuit.
• Design for 4-bit by 2-bit division explained:
  • D3 D2 D1 D0: Dividend (4 bits)
  • d1 d0: Divisor (2 bits)
  • Q3 to Q0: Quotient bits
  • R2 to R0: Remainder bits

Example Walkthrough

• Example: Divide 1010 (10) by 11 (3).
• First stage:
  • Compare divisor with first bits of dividend
  • Perform subtraction, determine borrow, update quotient
• Repeat process for each iteration until all bits are processed.

Simulation Results

• Simulation demonstrates division operations.
• Example outputs shown for various dividends and divisors:
  • 1001 (9)/11 gives quotient 0, remainder 1001.
  • 1011 (11)/11 gives quotient 1, remainder 0.
  • 1111 (15)/11 gives quotient 1, remainder 100.

Additional Considerations

• As bit numbers increase, processing blocks also increase.
• Future videos will cover sequential division circuits.

Conclusion

• Understanding of combinational circuit design for binary division.
• Encouragement to ask questions and subscribe for more content.