ARM Single Cycle Architecture

Overview

• Focus on ARM single cycle architecture
• Importance: Understanding how a processor processes information
• Example: ADD instruction (R-type) - add register 2 plus register 3, store result in register 1

Prerequisites for Tracing

1. Instruction Memory: Knowing the memory address storing the 32-bit instruction
2. Program Counter (PC): Contains the address of the instruction (e.g., value 12 in binary)
3. Register File: Need to know the state of registers being read (registers 2 and 3)

Instruction Memory and Program Counter

• PC Value: Starts at value 12 (binary)
• Address Increment: Adds 4 to PC value to get the next instruction address (32 bits per instruction)

Tracing ADD Instruction through Data Path

1. Fetch: Read instruction from memory at address 12 (ADD instruction)

   • Opcode: Bits 21-31 (ADD opcode)
   • Rn: Bits 5-9 (register 2)
   • Rm: Bits 16-20 (register 3)
   • Rd: Bits 0-4 (register 1)

2. Register Read: Values of registers 2 and 3 are read (e.g., 6 and 7 in base 10)

   • Mux Control: Selects correct input (register 3)

3. ALU Operation: Add values of registers 2 and 3 (result: 13)

   • ALU Control: Based on opcode, sets ALU to perform add operation

4. Write Back: Write result (13) to register 1

5. PC Update: Increment PC to the next address (value 16 in binary)

Control Signals

• Reg2Loc: 0 (read 2 registers, write 1 register)
• ALUSrc: 0 (uses both register inputs)
• RegWrite: 1 (writing to a register)
• MemWrite: 0 (not writing to memory)
• MemRead: 0 (not reading from memory)
• UncondBranch: 0 (not an unconditional branch)
• CondBranch: 0 (not a conditional branch)
• MemToReg: 0 (bypasses memory, uses ALU output)

Conclusion

• Understanding how to trace the data path helps in understanding how processors work
• Similar principles apply to other architectures like MIPS
• Future steps: Study other instruction formats (I-type, data transfer) and ways to improve processor speed