Overview
This lecture explains how to write and simulate a basic "Hello World" VHDL program, highlighting the structure of a VHDL file and key simulation requirements.
Introduction to VHDL and "Hello World"
- VHDL (VHSIC Hardware Description Language) is used to describe digital logic for FPGAs and ASICs.
- Writing a "Hello World" program is a typical first step when learning a new programming language.
- VHDL code is often run and tested using a simulator such as ModelSim.
VHDL File Structure
- A VHDL file must contain at least an entity declaration and an architecture body.
- The entity describes the module’s inputs and outputs and can be left empty for simple cases.
- The architecture contains the main code and describes the behavior of the module.
Creating the "Hello World" Program in VHDL
- Start by declaring an empty entity to meet VHDL requirements.
- In the architecture section, define a process block to execute code.
- The process block executes lines sequentially, even though VHDL is generally parallel.
Printing Text in VHDL
- Use the report statement inside the process to print "Hello World!" to the simulation console.
- Example:
report "Hello World!"; outputs the message when run in the simulator.
Wait Statement and Simulation Time
- Every process in VHDL must contain a wait statement to halt or control execution.
- The line
wait; pauses the process indefinitely, preventing uncontrolled looping.
- Without a wait statement, the simulator throws an error ("Process contains no WAIT statement").
VHDL Simulation Concepts
- Code in the simulator runs in simulation time, not real time.
- Except for wait statements, VHDL statements consume zero simulation time.
- Wait statements are required to advance or pause simulation.
Key Terms & Definitions
- Entity — Defines the interface (inputs and outputs) of a VHDL module.
- Architecture — Describes the internal behavior of a VHDL module.
- Process — A sequential block of code within architecture that executes from top to bottom.
- Report statement — Outputs text to the console during simulation.
- Wait statement — Pauses process execution and controls simulation time.
Action Items / Next Steps
- Practice writing a VHDL file with an empty entity and an architecture containing a process.
- Use the report statement and wait statement in your test VHDL code.
- Run simulations in ModelSim or a similar simulator to observe output and behavior.