Understanding ARM Cortex-M Load-Store Architecture

Nov 3, 2024

ARM Cortex-M Architecture: Load-Store Instructions

Overview

  • ARM Cortex-M Architecture is a load-store architecture.
    • Most instructions do not access memory directly.
    • MOVE instruction only accesses registers, not memory.
  • Load and Store Instructions are used for memory access.

Load Instruction

  • Uses a register as a pointer to a memory address.
    • Syntax: register enclosed in square brackets.
  • Example: Load value from memory address in register 1 into register 5.
  • Register Offset Addressing
    • Adds a constant to a register’s value to determine memory address.
    • Example: Adds 4 to register 1 to fetch data, copies into register 6.

Store Instruction

  • Source operand is the data source; Destination operand is the memory address.
    • Copies a value from a register to a specified memory address.
  • Example: Value in register 3 stored at address specified by register 1.

Literal Addressing Mode

  • Loads any 32-bit constant into a register.
  • Literal Pool: Memory area where constants are stored.
  • Program Counter is used to calculate the address offset.
  • Relocatable Code: Code can be compiled without knowing exact constant values.
    • Compiler uses a symbolic name for constants, e.g., .equ directive.
    • Constants are bundled with the executable code.

Comparison with MOVW and MOVT Instructions

  • MOVW and MOVT
    • Available from ARM V7 architecture (Cortex-M3, M4).
    • Not available on Cortex-M0.
  • LDR Instruction
    • Uses less program memory than MOVW and MOVT.
    • Can interfere with instruction fetches, potentially slowing down the processor.

Key Takeaways

  • Load-Store Architecture
    • Few instructions can directly access memory or I/O device registers.
  • Register as Pointer
    • Must hold the full 32-bit address for memory operations.
  • Literal Values
    • Placed in the literal pool, accessed with a program counter offset.
    • Enables relocatable code without storing constant values until final linking.

This summary covers the essential details of load-store operations and literal addressing modes in the ARM Cortex-M architecture, providing a foundation for understanding how memory and constants are managed within this system.