Lecture on Parasitic Delay and Driving Load Capacitance

Introduction

• Parasitic delay: Independent of gate strength or drive strength.
• Drive strength: Upsizing a NAND gate by a factor of K (every transistor is upsized by K).
  • Example: Input capacitance of a unit NAND 2 gate is 4C; upsized by K -> 4K C
  • Resistance drops to R/K.

Key Concepts

• Parasitic Delay: Remains the same regardless of gate upsizing (K's cancel out).
  • Delay = 7 RC or 6 RC regardless of drive strength.
• Approximation for Delay: Count capacitance on the output node and divide by diffusion capacitance of reference inverter.
  • Example: Parasitic capacitance = 6C, reference inverter capacitance = 3C -> Normalized parasitic delay = 6C / 3C = 2.

Upsizing Gates by Factor of K

• Capacitance: For an upsized gate, use capacitance of the inverter with the same drive strength.
  • Rule: As long as scaling factors for NAND and NOR gates are the same, it doesn't affect delay appreciably.

Driving Fixed Load Capacitance (CL)

• Scenario: NAND gate driving another gate (external load capacitance CL)
  • Not affected by drive strength of NAND 2.
• Equivalent Circuit: Includes parasitic capacitance + load capacitance.
  • Rise delay = R(6C + CL), Fall delay similarly = R(6C + CL).

Impact of Increasing Drive Strength (K)

• Gate upsized by K, transistors scaled by K -> Resistance = R/K, Parasitic Capacitance = 6KC.
• Delay Calculations:
  • Rise delay: (R/K)(6KC + CL) = 6RC + (R * CL / K)
  • Fall delay: Same calculation.
  • Key Insight: Parasitic delay remains constant, load delay decreases as 1/K.

Partitioning Delay

• Delay has two components: Parasitic Delay + Load Delay.
• Terms:
  • Parasitic delay - Fixed regardless of gate size.
  • Load delay - Related to charging of CL, falls as 1/K with larger transistors.

Further Analysis

• Definitions:
  • DUT: Device Under Test (upsized gate capacitance 4KC).
  • C_unit: Capacitance of a unit gate configuration.
• Normalized Delay:
  • [R(CL / C_DUT) C_unit + nRC] / (3RC)
  • Simplifies to: (CL / C_DUT * C_unit / (3C)) + (n / 3)

Notion of Effort

• Electrical Effort: Ratio of output capacitance to input capacitance (CL / C_DUT).
• Logical Effort: Ratio of unit gate capacitance to reference inverter capacitance (depends on gate topology).
  • Importance: Logical effort purely topological and independent of load/input capacitance.