okay let's get started is it all good okay okay we're going to continue well there's still 30 seconds or so let's make sure this is working it's working okay we're going to continue the third week's uh well start the third week of this lecture and remember that we were designing sequential logic and finite State machines uh today we're going to finish sequential logic design so you should be able to do both combinational logic and sequential logic uh and then we're going to talk about Hardware description language and ver log so this is what we covered in the last lecture green stuff all of the green stuff we've covered uh only the blue stuff is left oh thank you that's much better uh so basically we're going to design finite State machines today uh we kind of designed them last time but right now we're going to do it a little bit more rigorously fully but recall the first 10 slides or I'm going to jog your memory of what we covered we talked about sequential circuit sequential circuits essentially produce outputs that's determined by current inputs as well as past uh values these are circuits with memory and we actually built a bunch of storage elements uh to make this thing work right and and we had covered combinational circuits earlier and this was my analogy for combinational versus sequential and I think this really captures uh the memory aspect of a sequential circuit very well the lock uh over here the sequential lock on the right to your right uh uh has has some memory and we built a state machine for that sequential lock for a particular combination and uh you can see the state machine and we said that this an asynchronous State machine because there's no clock in this case there's no synchronizer if you will and you can verify the state machine yourself and we discussed what a state machine is State machine is really a pictorial representation of a discrete time model of a stateful system essentially uh and it has a finite number of states finite number of inputs finite number of outputs and a explicit specification of how you can go from one state to another state and an explicit specification of what determines each external output value and how it's produced and when it produced does that make sense so it's clear hopefully and this particular finite State machine has all of those characteristics actually uh and then we talked about how to build this uh basically we need three uh elements three circuit elements one is the state Register we talked about that this is how do you build the state Register so that you can remember uh the current state that you're in uh and then next state logic how do you go from one state to another state next state logic determines that and then output logic how do you produce the output uh of the finite State machine given the inputs and the current state and you can see that this is uh how you actually organize a finite State machine Any finite State machine can look like this I don't know what's happening anybody there's some timeout that is present somewhere here and that could be a finite State machine there you go the finite State machine is kicking in every maybe some synchronous clock okay but basically at the beginning of the clock cycle next state is lashed into the state Register and we actually spent some time to build the state Register because what we started out with the D latch or gated DCH was not enough right uh so we built the sequential circuits as well as a combinational circuit so we said remember that how do we implement the state Register so that it it has two properties one is uh the data gets lashed at the beginning of every clock cycle and the data inside the state Register is available for the full clock cycle full duration of the clock cycle so that the combination Logic for the next state logic as well as output logic can evaluate for the full clock cycle and they can settle and this is going to be very important for the timing lecture that we will start tomorrow we're now ignore the timing we want this desired Behavior how do we make it happen we said that the latches that we designed until that point in time are not good enough because they're transparent what does transparency mean transparency means that whenever uh the uh input value changes uh while the clock is high the output value also changes so this violates what we want to do what we want to do is we want the clock we want we want the input signal to affect the output signal only at the clock Edge right and available for be available for full cycle and then we develop the D flip-flop so hopefully you can see that the state changes on a clock Edge in here now this is really annoying some clock had just happened for example okay well maybe it'll keep you a wait or maybe it'll keep you away from computers once in a while okay I see a lot of people paying attention so that's good so basically State changed on a clocked and the data is available for full clock full cycle because what we did was we actually had a let's say Protector first latch uh behind earlier than the second latch and this ensures that uh whenever the clock uh uh changes when the clock is low for example the first SL propagates the value of D to the output of here and whenever the clock changes from low to high that's called the rising edge of the clock the value of D that was propagated here gets propagated to Q because of the way clock is wired as you can see to the right enal signal of the first latch and the right enal signal of the second latch clock is basically uh this is really annoying uh you you cannot see it right we need to fix this somehow uh so when the clock is low d goes here when the clock is high when it transitions to high that capture d goes over here okay so that's the D flip flop we actually covered this last time I covered a little bit more because it's important and we can actually use these D flip flops to implement the state Register as many uh def flip flops uh in parallel as you need essentially and I'll show you that in a little bit but just to summarize this was the last slide we covered uh in the last lecture uh we say that flip-flop samples the input D on the rising of the clock or positive edge of the clock you can easily design a Negative Edge triggered D flip flop also but this is a positive Edge triggered D flip flop uh yeah and I think we said everything uh over here so this is an edge triggered State element because it captures a data on the clock Edge as opposed to a latch which is a level triggered State element which captures data on a level for example when the clock is one or when the clock is zero depending on how you tie the right enal signal to the clock uh different levels of the clock uh can actually uh enable State transitions so we want these Edge trigger State elements in our finite State machines for the reasons that we discussed earlier so how do you build basically a d flip flop based register is very similar to another register uh that uh you use we used we did we did build using latches except now we use def flip plops so this picture shows you four D flip plops so this is a 4-bit d flip flop based register and you can actually uh indicate it this way uh this is one representation of it this register stores four bits and you can see that uh output is four bits also this line represent four wires that's what this four over here means with with a slash on The Wire so you'll see this terminology uh uh a lot and this is from your other book uh patam Patel book that basically shows essentially the same thing but it shows the internals of the D FL flop and you can see how expensive this is right there as I said there uh there eight Gates and there uh how many transistors would we say over here so one n gate is four transistors right so we have how many transistors does anybody want to venture so for uh for for for one of these uh de flip-flops we have one two three four Nan Gates each of them has four uh uh transistors that's 16 and then you have an inverter over here that is kind of high that's 17 and then you duplicate that that's 34 so each of them has 34 transistor that's a lot right and we compare this to Dam that has only one transistor okay if I made the mat wrong please shout it's okay so nobody objects okay okay uh so basically uh now let's actually build a finite State machine uh based on what we we've learned we're not going to go into the details of the flipflop anymore but you will do this actually in your Labs we're going to get back to it in the later part of this lecture when we talk about VAR log and Hardware description languages we're going to figure out how to write this exact same thing uh in a hardware description language called verog it's going to be very easy actually you don't need to worry about the internals especially when you do the behavioral modeling if you do the gate level modeling as we will see later on that's called structural modeling you will need to know the structure but if you do behavioral modeling we're going to abstract it away and you don't need to know the underlying implementation but now you know why it's important to know the underlying implementation right how many gates could could it be implemented with okay so finite State machines we said that next state is determined by the current state and the inputs and there're actually two different types of finite State machines depending on what the outputs depend on in a more type of finite State machine the output depends only on the current state so output is really solely a function of the current state and we will see this and we will also see a melee type of finite State machine where the output depends on the current state as well as the inputs okay so this is the way you design the machine actually State uh uh basically in the more type of machine State directly indicates your output in the other type of machine just by looking at the state you don't know you don't know the output value you have to know the transition from the state you have to know the input that goes into the state as well and this has trade-offs so let's take a look at one finite State machine example from your book how many people have seen this okay that's good you're you're reading the book I guess uh or maybe watch the lecture from the past how many people are reading the book okay that's great yeah okay so basically this is a supposedly smart traffic light controller which is actually not so smart as we will see but it's trying to be smart at least different from the traffic light controller that we've seen earlier so in this particular case we have two Avenues Avenue a let's say and then Avenue B or Boulevard B A and B let's say and uh the traffic light there are four traffic lights as you can see over here uh and there are two inputs and two outputs to each traffic light uh there are traffic sensors on Avenue A and Avenue B and these traffic sensors are one bit inputs and they respectively turn two when there's traffic on the corresponding Avenue or corresponding Road let's say and they're false when there's no traffic on the corresponding uh wrote and there are two outputs these are the lights basically LA and lb and la and lb are actually I said four lights but the lights on the academic Avenue are the same and lights on the bra Avenue are Boulevard are the same over here and each of them have three states as we have discussed these are Swiss traffic lights as opposed to Texan traffic lights there are three states red yellow green if you were living in Texas it would be red and green there would be no yellow uh you could make an argument as to which one's better but we're going to not talk about that uh State can change every 5 Seconds that's our assumption but there is one butt over here uh except uh if if you have traffic uh on an Avenue and if the light is green State doesn't change you stay at Green so this is the smartness not so smart in one sense because if you keep having traffic on one Avenue that Avenue will stay green forever right so you will get denied service on the other Avenue so this is actually an interesting design thing whenever you're scheduling you need to be careful about fairness and quality of service so this traffic light doesn't satisfy fairness and quality of service requirements or definitions it just says if the light is green and there's traffic on this Avenue that Avenue is prioritized over the other one live with it so the people on the other Avenue can go crazy fine that's that's the traffic light that your bookas and this is basically a black box of the finite State machine that we have you can see that all finite State machines have to have a reset state that basically uh tells you where you start the system when it's reset like when you power it up for example so don't ever forget the reset State because uh the system is completely undefined if you don't know uh when where to start from basically to begin with right so if I don't know how to start this machine what is the reset State then this machine can give me all kinds of junk output in the end right so this is critical and there's a clock as we said because it's a synchronous finite State machine and then there are two inputs uh these are the traffic sensors and then there two outputs these are the lights on the two different roads okay I've already said all of these I think yeah now let's take a look at let's construct this finite State machine diagram relatively quickly we're going to construct the more finite State machine but you could also easily construct the melee one states are going to be circles this is our state zero uh the light on Avenue A is GRE the light on Boulevard B is red it just happens that way and it happens that we're prioritizing that one in the beginning reset when whenever you reset you go to that state transitions are basically arcs so reset clearly causes some transition basically you go into the state from an undefined point uh whenever you start and then you're not seeing that but now you're seeing it uh whenever there's traffic on Avenue A and the light is green you stay in state zero as you can see when there's no traffic on Avenue A you go to state one and state one basically changes the light so that Avenue B can take over at some point so you can see this is yellow and red now and then going from State one to state two is unconditional it doesn't matter what the lights are you after at the next clock Edge uh you go to state two where the light on Avenue A becomes red and light on Avenue B becomes green and then the same thing happens basically if if traffic uh is there uh at the clock Ed at the next clock Edge uh you stay in state two otherwise if if traffic is there on Avenue on bouard B at the next clock you stay on state two otherwise you transition to state three and then the the transition from state three to state zero is uncond conditional again uh because uh yeah because this is an intermediate state where light B is yellow as you can see so this is a more type of finite State machine because States clearly indicate what the outputs are outputs are solely dependent on which state you're in so outputs don't actually happen when you go from one state to another state based on some input so if you look at this and if the outputs are indicated inside the uh State circles over there you can say that it's a more type of machine okay everything good so based on the specification you can design a finite State machine and that's what we did basically you can say specification is not great so I'm going to enhance the specification in some way can we easily fix this problem because it's getting really annoying is it annoying for you guys yeah I think so I don't know how to easily fix it uh I guess one option could be I could present from here but okay while you're doing that we need to go to okay you need to to share the screen to share the screen okay okay let's do that but can I quickly do that I guess I don't know okay okay maybe I'll take questions in the meantime any questions so what we're going to do is basically we're going to build uh essentially the output logic next state logic as well as uh state Register any question any question so far you have yes please other types of fin engine other than more and M I mean there are other classifications like synchronous versus asynchronous like we discussed time right it requires a clock whereas the sequential lock finite State machine was an asynchronous finite State machine so certainly yes there are other types of finite State machines I would say but in terms of how outputs uh are generated B based on the dependence on the state versus State and inputs it's just more and Mele any other thoughts okay good let's open that this works thanks okay this thing is also working so I can see myself too okay so now let's build the F any any other questions now that we've started questions okay good so we've switched the finite State machine as you can see right something that's controlling uh uh you can also do that right you can switch the finite State machine dynamically in a machine in a real machine and we will see that later on okay let's build the fin a state transition table so we have the State transition table now let's actually turn this into a truth table right we know how to do that basically uh this is we're going to decide the next state logic next state logic as we said is a function of the current state as well as the inputs So based on what we built uh this pictorial structure uh if the current state is S zero and if there's uh no traffic on a then the next state is S1 right so basically you can build the truth table relatively easily by just looking at things again this is a butchered type of truth table it's a compressed type of truth table right I don't have ones and zeros I don't have every possible input value but I'm going to expand to that in a little bit and I also have don't care as you can see right I don't care what the uh traffic sensor on Avenue B is in state zero because you can see that TB is it doesn't determine anything any transition from state zero if the uh State current state is a state zero and there's traffic on uh uh Avenue a it doesn't matter what traffic sensor on Avenue B B is the next state is still L to you so you can basically keep doing this and then this is an unconditional transition as you can see if the current state is S1 it doesn't matter what the inputs are the next state is always S2 at the clock Ed you switch you you change to that next state now let's encode these states we're going to talk about encoding later on but you can choose one encoding this is one encoding since we have four states we need two bits right that's the most compact encoding and I I assume these two well your book assumed these two values now you can actually write States as two bit uh input two bit values let's say that are stored in the state Register and basically I just replaced s0 with 0 0 S1 with 01 S2 with one zero and S3 with one one everywhere inside this table now we have a much nicer tooth table and now we can actually Express this in terms of Boolean logic right S1 Prime this bit of the next state is one now we're doing this uh sum of products uh form is one only for these input values meaning uh S1 Prime is one for uh if S1 is zero and s0o is one and this doesn't matter so you can actually write this you can see that these are the uh these are the implicants uh well I would call that implicants these are the values of the input variables that correspond to S1 Prime being one right S1 Prime is one if this is true or if this is true S1 is one s0 is z and TB is one and it doesn't matter what this is and this is a sum of products form or somewhat reduced sum of products form because we have don't cares over here uh of uh essentially this function s One Prime and you can do the same thing for s z Prime you can see that s z Prime is one only for these uh values of the truth table this compress truth pable if you will and that corresponds to uh S1 S2 ta s0 and ta all being zeros and S1 being one s0o being zero and TB being zero and these are the uh sum of products form essentially again considering the uh don't cares so everything we learned in combination logic and logic simplification also applies here you can simplify this and this becomes S1 xor S zero and the other one unfortunately you cannot simplify it further so that's our next logic basically does that make sense this is how you determine next state based on the current state and the inputs now let's take a look at the output table we're going to do the same thing essentially uh well something similar not exactly the same thing of course uh as we said output this a more type of machine so output is solely a function of the current state that's why you don't see the inputs uh to the finite State machine on the left hand side of this truth table again and if the current state is S1 current state is 0 0 S10 s0 0 then the La is green and lb is red so you can actually verify this now you need to encode the outputs of course because green and red doesn't mean anything you cannot simplify that you need to encode green yellow and red and again these are three there are three types of three outputs so you need two bits to represent them in binary and then you basically do the same thing you try you start simplifying la1 is one ifs1 is one as you can see right so we quickly did that simplification over here based on the uniting theorem right you remember uniting theorem says if uh for for the onset of a function in this case the output is la1 if an input changes uh and it covers all of the possible changes in binary in this particular it does then you can eliminate it so s0 can be eliminated so la1 is represented as one and la0 is one only in this case S1 z s s z is one and this happens to be L B1 is one uh when S1 is zero so it's S1 Prime as you can see this again based on uniting theorem and then lb0 is expressed this way so this is the output logic as you can see so each bit of the output is determined as a function of the bits of the state makes sense right okay so there's no magic as you can see right any finite State machine you can reduce it to a through table once you have the once you have the pictorial uh State transition table and once that's correct and complete you can reduce it to a truth table and then you actually optimize the uh you can actually Express the next state logic and the output logic which is what we did right now okay let's take a look at the schematic right now so this was our finite State machine uh General our state Register is going to look like this basically uh it's a two- bit state Register and this is the current state on the right clock reset and then this is the next state on the left next St bits coming in on the left and there will be a logic that determines next state bits as we discussed and this is the logic that determines the next state bits based on what we did earlier right for our traffic light smart traffic light I should say uh okay so hopefully that's clear and this is the output logic basic output logic is solely a function of S1 and s0o inputs doesn't matter over here for the next state logic you can see that inputs ta and TB mattered obviously but because it's a more type of machine uh the next state logic uh oh output log is only dependent on the current state okay no questions we can move on so this is something I'm not going to cover in detail but this is good to think about this is a timing diagram based on some inputs we're going to cover more on the timing diagrams tomorrow just this is just to jog your thinking a little bit so you're in this current state uh and then uh inputs um now something is happening over here you can see that reset reset basically resets the current state right at some because reset is high you reset the current state and you go into the state and this happens to be actually uh a flip-flop with an asynchronous reset because the reset takes effect almost immediately regardless of the clock Edge uh so we're going to talk about that when we talk about the very log lecture so reset doesn't depend on the clock basically whenever you reset the machine doesn't depend on the clock so this is not a completely synchronous system from that perspective but we will talk about that when we talk about uh flip-flops in uh Hardware description languages and then you can see that uh you're in state zero over here and it happens that ta is one so you stay you still stay in state zero over here and then ta becomes zero right at the clock Edge over here so you transition to State one over here and takes some time so transitions actually take some time based on the combination logic delay because there remember there are two types of combination logic over here the next state logic what is the next state going to be and what is the output going to be output logic right and because there are nonone zero delays that you have in these Gates that for example the end Gates earlier or end Gates it takes some time to transition from state to state so it takes some time for the outputs and the state to change and that's what this delay is and we're going to talk about that a lot when we talk about timing and verification this is just to prepare you for that and you can see that transition from State one to state two is unconditional it doesn't matter what the inputs are TB is one for example it doesn't matter you trans position to S2 and then you can see that yeah yeah next state stays in S2 because TB is one uh while you're in S2 and then you transition to S3 uh when the TB uh becomes zero at the next clock Edge it just happens to be become zero over there okay and then there's some transition delays so if you want to go through this in full you should look at uh H&H chapter 3.4 it actually has this demonstration but uh we will see in timing and verification so this means that uh if you want to properly transition if you want to if you want this to work correctly your clock cycle should be long enough uh to accommodate the delay of the combination logic and the latching that we have right this is really critical if your clock cycle is so short that the combinational logic takes longer time to settle to evaluate to uh to evaluate it uh outputs from from the time inputs change then you will not get a properly working system that's the importance of timing your clock cycle should be long enough to accommodate the longest combinational logic delay that you have in your system and we've actually seen that combination logic so let's go back uh so this is the there are two combination logic one is this your clock cycle should be long enough such that uh after uh t t ta and TB change and one and S2 start propagating this delay over the circuitry uh settles basically your clock cycle should accommodate the delay of the circuitry as well as this circuitry over here if your clock cycle is uh Too Short over here you will get the wrong output in a given state right here if your clock cycle is too short you will change the state to a wrong State potentially or you may not change the state uh because you didn't give enough time for the circuit to actually uh finish evaluation and get its output latched in the state Register okay now I introduce some timing into this right so far we've been very logical but timing is really important in these okay okay so let's go over we're going to see more of this and we're going to see actually in timing and verification that it's really a sequential system that we're talking about a sequential system uh beginning of the clock cycle ending of the clock cycle there's some combination logic and you have to accommodate the long combination logic delay if you cannot accommodate it divide the work into multiple different uh let's say clock cycles and we will see that when we talk about pipelining for example later on in the principles of design of uh uh micro architecture so I'm kind of getting ahead of myself but this is this all of this is actually will be building up to a microarchitecture that processes instructions and that instruction processing can be done in one single clock cycle as we will see and we will see that that's very long clock cycle so we're going to chop it into pieces such that your clock cycle can be shorter but now you need to design a finite State machine that process instructions in an appropriate manner in multiple clock Cycles so whatever we're going to see in a few lectures is going to build directly on top of what we're seeing right now okay so State encoding so we just assumed some State encoding how do you encode the states and then we just assume some output encoding how do you encode the outputs uh so basically uh there are three common ways of encoding states with different trade-offs I will not go into a lot of trade-offs over here uh since this is not a again logic synthesis or design optimization course but just to give you an idea they're fully encoded one hard encoded output encoded fully encode also means binary encoded so let's take a look at our Swiss traffic light again you can see that we have four states over here and this is a pictorial representation of it binary encoding full encoding means that use the minimum possible number of bits if you have for state in binary uh minimum possible possible number of bits is log 2 to the four uh and that's basically two right and then you can assign some encodings over here uh this minimizes the number of flip-flops that you have clearly but not necessarily the output logic or the next state logic so that's the trade-off basically you minimize the state elements but now your combination logic may be bigger so there's a trade-off over here which is interesting of course in the small circuit it may not matter that much but in large circuits this may actually matter especially in large circuits with many many many states if you think about a processor today it has millions of States maybe actually even much much larger than Millions an understatement if you will okay one hot encoding basically here each bit encodes a different state uh you use the number of states to bit number of bits to represent the state so you have four bits basically in this particular case and exactly one bit is hot or one for a given state so you can see that 0000001 uh represents one State 00 1 Z another state 0 1 0 Z another state and one 0 Z another state so this is nice because this is very easily automatable uh it's a simplest design process you know exactly which bit is set for a given State uh unfortunately this maximizes the number of flip-flops but uh as I said it minimizes it is actually very automatable as well as it minimizes next state logic so next state logic becomes much simpler right now so they're trade-offs as you can see and the final ones I'll put encoding here outputs are directly accessible in the state encoding for example if here we have three outputs right uh that's the light color uh we encode the state with three bits where each bit represents a color so you can see 0 0 one uh Bit Zero encodes the green and bit bit one encodes yellow this is 0 one Z that's yellow and bit two encodes uh red that's one0 and then there's another state that has both yellow and red and that same quote as one one Z so in this case outputs are directly accessible uh from the state and this works nicely for more machines because more machines in more machines outputs depend only on the state not on the inputs clearly if outputs dependent on dependent on the input you cannot do that right you cannot encode the outputs inside the state encoding itself right okay so this this is also good this minimize the output logic but as I said uh it has some limitations so next state logic is another issue over here which we're not going to discuss so basically uh it's the job of the designer to uh carefully choose an encoding scheme to optimize design under given constraints again automated synthesis tools do some of this but if the circuit is very very large as we will see later on it's designer actually is an important uh let's say participant in the process of optimization any questions okay hopefully these are not too bad so Mo versus m machines going back to Mo versus m let's design uh a couple of things uh again based on your book uh this is just a reminder more output depends only on the current state and mely output depends on the current state as well as the inputs and your book has an example how many people remember the this Example The Smiling snail no one okay some people that's good so basically you're designing well you're you're modeling in this particular case you're not designing the snail you're modeling a snail's brain and the snail happens to be a somewhat intelligent snail it's it's able to interpret uh the bits or digits that it uh crawls over and if it actually sees a sequence 1101 it basically Smiles magic right uh basically you're modeling the snail's brain how do you do that you could do it with a more FSM or Mele FSM uh so basically uh if if someone gives you this problem of modeling you design this as a state machine right the the snail Smiles only when it sees one one Z1 in a sequence and otherwise it doesn't smile so smile is an output it's one only in this particular state where you reach after seeing one one zero one right and then after that whatever you see brings you to the reset state so you have to have a reset State as you can see and here we have five states in the fifth state over here you know that you have seen one one zero one in sequence and then this state uh directly corresponds to the output smile and that's one every other state smile is zero meaning the snail doesn't smile and you can make sure that this works and it works uh mfsm on the other hand uh looks like this we didn't design this so far but I want to introduce you to this one also but basically here you have four states only so it actually reduces the number of states as you can see but uh reset is here you have not seen anything assume that nope so if you've seen a one the output is zero the smile is zero so this is the input this is the output and you go to state one and state one basically says you have seen a one and you see another one the output is still zero you go to state two and you see a zero the output is still zero because you have seen the sequence of one one zero right now and that's what the state means now if you see another one you go to this state and you output one so basically you can play tricks like this you can actually combine different states over here because your output is now in dependent well I just say independent or partially dependent on the state right partially depend on the previous state you were in and the input that was applied to the previous state right so basically once you see one one zero one you're at this state and your output is one and then you can basically keep emulating what it does so I don't want to go through the details of this detail of the state machine uh but you can see that there are some trade-offs over here with M fsms because the output is uh not solely a function of the States you can actually reduce the number of states but your output logic may become more complicated uh this way but again in big machines this may matter okay so we may ask you to design finite State machines and actually you will do that in your Labs especially but who knows maybe in the exam also this is not a difficult procedure as you've seen right with simple finite State machines it's not that hard you need to determine all possible states of the machine you need to develop a state transition diagram uh uh and this is generally done from a description of what should happen and clearly this should have everything inputs outputs for each state as well as how to get from one state to another and don't forget the reset reset is very important and as I said over here uh yeah I don't know if I want to go through all of these over here but I will mention that this is building an FSM is kind of like programming right like what do you've done over here in modeling the uh brain of the snail is kind of if the input sequences one one Z one you output a one right you can actually write a program that does this relatively easily except we're doing it as a sequence of States not uh not not as a uh let's say program that you're used to so it is not programming basically you're really designing a stateful system in the end uh and as I said as I just mention gave an example of it has a sequential control flow like a program with conditionals and goto for example if I'm in this state and if I've seen uh a digit one I should go to this state otherwise I should stay I should go to this other state for example right so basically you can actually Express a finite State machine as a program it's not that hard yeah I think I've said this if theal Constructor is controlled by one or more inputs and the outputs are controlled by the state or the inputs basically in Hardware you typically have many such concurrent finite State machines and we're going to see that again next week uh one of the finite State machines may be decoding instructions another finite State machine may be controll the execution of the instructions another finite State machine may be actually controlling what's happening in the accelerator over here another finite State machine may be controlling what's happening in the M site another finite State machine may be controlling the SSD so you actually have a b bunch of finite State machines that interact with each other and overall it's actually a huge finite State machine that you can model but you really normally build hierarchy of finite State machines when you build Hardware because clearly designing a single finite State machine for everything that goes on concurrently is very difficult right I mean you can imagine again the each of you as being finite State machines and you're interacting with each of you who different finite State machines over here also right you could try to model everybody together in this room as a single finite State machine you would be probably plucking your hair by the time you're you're you're in the middle of that or maybe five seconds into that but it's a lot easier to actually describe each one of you as a different finite state machine that that's interacting with uh others okay any questions okay so what is to come basically we're going to see the finite State machine of this one I didn't show you over here but you can take a look uh this is going to be basically what we have done so far is build up the fundamental blocks starting from the transistor combination logic sequential logic we're going to see all of these basically you can see that there's some uh State element over here register file there's some memory over here input output there's a bunch of combination logic that we will see over here this this going to be a finite State machine we're going to design actually this lc3 processor that can process instructions from a small instruction set and you're going to do something like that in your Labs as well and this is going to be the data path that we we're going to see and build you can see some of the elements that we've seen so far multiplexers for example there's a decoder somewhere that's not shown over here but we're going to use everything that we have used so far you can you can actually see the high State buffers over here right and then there's a bus over here uh and uh these Tri-State buffers control what data value gets loaded get uh loaded onto the bus again that's a teaser we're not going to go into that right now but I think this gives me a nice time to uh give you a 10-minute break does that sound good let's take an early break right now and we'll be back in 10 minutes to start lecture five okay um let's get it started again is everything going fine uh on Zoom uh YouTube yeah we had some infrastructure issues but things are I guess under control thanks to our great T great um so I think this is also a kind of lecture that you guys uh we've been waiting for it I'm going to uh introduce you the labs and also provide some fjs I put U ater's name actually here on purpose because he actually he's the main uh person for labs and he's leading Labs he's also attending this conference to present uh HBC conference as I said to present his paper so yeah but in general when if you have questions about Labs you need to I mean you can of course uh come to me but atre is the main person essentially okay so we're going to see about logistics first um our lab session you know that is on site and we have uh four days this information is already known for you so I'm I'm not going to bore you and uh basically we have these times and also these rooms just make sure that in Friday the first session uh we have different rooms so this should be easy for you to cover and the first session is going to be next week on Tuesday so make sure you attend I mean those people that going to attend Tuesday session entally and you know that you will work in groups of two we had two options which I think we are already aware of that so things are already defined and uh every group will receive an FJ board to work with so make sure that you attend the first week of the lab I mean you should attend all the lab session but first week is also important because you're going to get a FG and please follow models for details um the grading we have 10 labs and we have 30 points in total so you know that 70 points is coming from your exam and 30 points is coming from your Labs so with that we're going to have 100 points that it's going to somehow scale to one to six so we we will put the lab manuals online on our web page uh and this grading policy we have inclass evaluation like lab sessions evaluation which is 70% and mandatory lab reports which is 30% and they're going to be one point penalty for late submission of the report so you should finish the labs within one week after they are announced you can also use your grades for labs from past years uh this for example the Moodle page for last year we had actually in the past we had the students that for example in 2023 they wanted their lab grad from 2019 you know so don't worry we have database we can fetch from I don't know whenever you want just uh let us know exactly essentially and for question you can um email us um using this um basically mailing list uh this will email all send to all T essentially that we can and also we going to have model for so what we will learn in these lab sessions we're going to see about this transformation hierarchy and we're going to understand this S software Hardware interface micro architecture and logic specifically Labs so and how to make TRS between performance and area complexity in your Hardware implementation there are hands-on experience on Hardware prototyping using a fjs and debugging your Hardware implementation um using Hardware description language HDL which specifically we're going to see very lock uh how to use it and this Hardware design flow and as well as computer a design tools uh short as cat cat tools so what is an f f is States stands for field programable gate array this is one example of PGA there are many many different examples also in the market in the world you can see FJ is a software reconfigurable Hardware substrate that makes FJ so ex exciting because there is a chip but that chip is not hardcoded essentially so you can Implement kind of any circuit as as long as your circuit can fit in that FJ because each FJ has limitation in the number of look up tables number of I don't know flipflops multiplexer whatever so each FJ has a limit but with within that limit it can Implement everything that you want so this has reconfigurable functions reconfigurable interconnection of function which is very very important we're going to see bit why but you you have a lot of switch boxes you have a lot of switches that they call switch box connection box and all these switches can be reconfigured in order to connect a logic block to another logic block which is very important for fpj to uh Implement your circuit and also we have reconfigurable input and output uh in fpg so you have already seen this uh slide from Professor M's lecture that essentially we have this flexibility uh from CPUs and this is quite programming is but as we go uh through this um basically Spectrum you're going to see more efficiency but at the same time you might have basically less programmability so f is is they are standing kind of in midle between complet A6 and also something also after gpus that they are accelerators so we have a fidget in today's system these are some uh slid that I just want to motivate that uh a f that you're going to use not exactly the fij that you're going to use but the concept uh is very useful and many systems are actually using a f modern F this is one example in that used for deep learning platform and for f and this also from another system that they use FJ to solve complex science engineering business problems that require High bandies enhanced networking and very high compute capabilities there's also another FJ use for DNA sequencing which is important for genome analysis by informatics you may know uh when you want to that can actually um provide a lot of applications including uh personalized medicine to also you know to limit I mean mitigate this outbreak of our disease U so all these are important in genome analysis and DNA sequency is also one of the one of the very very early stage uh step of that so fjs are very useful for that as well and uh we Al we have also in our group we have used fjs in many of our studies these two papers gatekeeper and Sneaky Snake uh both of them are actually FJ based accelerators for bioinformatic applications and you can learn more about it by checking this paper uh we also use U basically f for other applications again this also based color for genomics we also use fpj for U weather prediction stencil applications uh so these are different application that essentially you can use a FJ to accelerate them you don't need to know all details of course about them just these slides are here just to motivate you to say see that you how a fjs are can be useful um for import to improve performance uh in our group we actually we have developed a system called the in in the past we were calling it soft MC but we actually extended much more and we improve it and now the name is actually Dam Bender um at is the leader for this project actually so that's why um he's also your head TA in this Labs um so this is an open source FJ based infrastructure to experimental studies on D so you can actually do a lot of studies um on DRM which using this dram vender which is kind of for example you can play with all timings of your dram your commands that you can uh you're sending to dram and that can help you to understand many of hidden stuff in your Dam and also design techniques uh in order to benefit from functionalities that they are actually already available in dram but people may not be aware of that so for example in one of our work recent work we show that um commodity of the sh dram chips they are capable of doing computation they are already capable of doing functionally complete um Boolean logic so you know what is functionally complete right so you can Implement n nor and or and not operations using commercially after shelf Le and chips so that's what we for example got from this D Bender uh system so you can also if you're interested you can check soft MC and D bender on our GitHub page is already completely released and this is also the paper if you want to learn more about it this is also one of a picture from this system you can check and this also this row Hammer study um that the first paper that we publish in this area that we show that essentially by uh opening and closing or activating and deactivating a a row in a dam row multiple times or let's say fast enough you can actually cause errors in adjacent or neighboring rowes in the so that's a phenomena we called it I mean they called it as RW Hammer it's called as RW Hammer that um that basically breaks one of the main importance like this isolation um principle of dam chips so you can actually by activating and deactivating one Dam row you can cause errors and later works they use this phenomena to actually design attacks security attacks so this is roham that you probably know about it because from Professor mlus talk um but basically we use our system to have lot more deeper look in raw hammer and also uncover a lot of um stuff about Ro Hammer as well as one of the technique that's basically industry provided and they thought they actually claimed that this solved the problem rammer but later on with this work and other works we show that this is not the case so yeah essentially uh you can use this kind of D Bender um infrastructure to do a lot of studies there's also another work that our in we publish in 2023 that we can we show that actually that there is also another phenomena called R press we actually call it R press that if you keep one row uh in the Dr active for a long time that can actually um cause errors in neighboring rows so we call it R press and we also again use Dam Bender you can for example Generate random numbers um inside your D and random numbers are important for many many applications so we get to this um you know generation of n random numbers in D I'm using this Dam Bender infrastructure okay so I don't want to bore you more but uh this kind of U infrastructure also can be used for other memories for example this one is for characterization of flash memories and it's actually from quite past um in 2012 uh until 2018 or so that we had this kind of infrastructure that we studied flash memories and we uncover a lot of reliability issues as well as mediation techniques for uh all these reliability issues in the flash memories uh of that time essentially if you want to learn more also about Flash memories like this error characterization of flash I would recommend you check this paper flash memories are really exciting um it's actually one of the very I would say uh nice lesson uh for for every researcher because when people were working on flash memories in 1990 or so so flash memories are way behind of their performance back then and many there were many people that were saying that why you are working on this kind of Technology this not going to work at all and uh but now you can see that those people were completely wrong so you had to actually work on these emerging memory Technologies to make them possible that can actually change many people's life and now the the main reason that for example we have a smartphones is flash memory otherwise you could not for example have a hard disk drive in your smartphone you know and then gets you know that rotate in your pocket uh to have your memory essentially so it's very interesting to see uh why we we need to work on emerging memory Technologies okay uh you can also use a fidget aot uh for Prototype this one example that we designed a prototype um in order to use processing using D so we show that for example we can have a holistic n2n fvj based framework for processing in D that you use your Dam in order to do computation you may not know completely what does it mean exactly but essentially you are using your dram to do computation and uh this P Dam you can actually Implement them in a prototype this the whole system is closed you can see you can implement the whole system essentially okay and these are also for another work metais and you can see that at work here this guy um he got this best paper award at high peak for this work okay so let's um have an overview of our lab exercises any questions by the way good so this is our FJ board basis three um this is actually is not a bad word I mean it's quite capable but of course it's not uh you know as capable as modern fpgs that people use but you can learn a lot of fundamental things about these fbgs so there are many actually um stuff going on this F you have USB connection you have video out VGA you have Micro USB you have power switch you have seven segment displays these are a lot of LEDs that you have you have switches that you can control use them as an input for example you have push buttons and this is your refug chip this you shows that you know when you want to design a system there are that the brain actually usually is so small and there are many many things going on you know around it uh to make interface and that's why actually interfaces are actually very expensive in the computer system okay so at the end of exercises we will have um built a 32bit microprocessor running on the FJ board so it will be a small processor but it will be able to execute pretty much any program so I think this is very exciting that we will learn how to design uh microprocessor and each week we will have a new exercise that in the end will guide you to that microprocessor essentially so you're also encouraged to experiment with the board on your own we may have some extra boards for those who are interested uh unlike ly I would emphasize on that but you can ask of course um and we see and it's not possible to destroy the board by programming so don't worry okay so in lab one we're going to draw a basic circuit uh it's going to be about comparison so you just need to draw a schematic of that circuit and we don't have a FJ programming involved in lab one but we encourage you to do it later uh and you have understanding of fbgs in lab two we want to map our first circuit to fbj uh we're going to start with addition which is very simple and we design a circuit that adds two one bit numbers which going to be a full add and then we reuse this one bit full adder in order to make 4bit addition and essentially you need to implement design a FJ board and you use input switches that I showed in that picture there are some switches that you can use as the input to the fij and also the output of the fij go to LEDs so you can see the output on those LEDs you know based on the lights that they are Lighting in lab three you're going to use actually um seven segments in order to show the result of lab two essentially so that's uh train you how to design a combination of circuits uh for fbgs in lab four we're going to design a fin ad estate machine that we Design This blinking LEDs for a car uh term signals and this Implement and basic implementation and use memories because kind of a sequential circuits and also we should be able to change the blinking speed so you're going to see in your lab material essentially in lab five we're going to see uh how to implement an ALU and that's actually the first kind of Step In order to get to your processor so you will design your ALU that can do some arithmetic operations like addition subtract multiply compare and some logical operation like and or and so on so forth then in lab six we're going to test our ALU um basically whenever you design you need to verify it and that's the verification part that you need to design kind of test PCH uh to simulate your U design and in lab six the focus is to teach you how to simulate and test the functionality essentially so we learn how to debug your implementation and to resolve problems essentially in lab seven we're going to write an assembly code for the microprocessor that we are looking for we will use a mips and that implemented program which you will later use to run on your processor which it sounds quite exciting at least to me in lab eight we will use we will basically make this full system integration we will that this will cover in two weeks so essentially we have 10 Labs but lab eight is actually kind of two Labs so we have lab 81 and lab 82 essentially and then we learn how a pro processor is built and we will complete your first design of a mips processor and we run a snake program on it for example like this okay and in lab n we analyze the performance of the processor that we design and how we can imp improve the performance by adding some other instructions like multiplication bit shifting and so on so forth okay so that's all but you can see the material for every lab we will put it on website you will check it I encourage you to check it early enough and you attend the lab session by kind of you know prepared mind as much as possible okay let I will also provide a bit more detail about fjs so what is an FJ we already know that it stands for field programmer gate array and you know this stuff so this is a high level overview of fjs that we need to configure logic blocks so all these um rectang squares let's say uh they are kind of logic blocks that you need to configure them uh in order to implement some functions and then you need to configure also these switch boxes or switch blocks essentially in order to make connection of these circuits and then you have some iocks and uh basically that you can use them you can again also configure them in order to see the output like when you check the data sheet of FJ you know that you're going to see that for example some of these these ioads uh they are connected to some of some outputs in your board like some of them are connected to seven segments some of them are connected to for example LEDs some of them are to switches so you can actually configure them nicely there are two main building blocks in f f look up tables and switches and I gu I mean you already know about lookup tables uh it's a Memory uh that you can Implement like when you have Lut of three input you can essentially Implement any three input function using that Lut so and then also you have switches that you can configure them in order to make connection essentially so this is a three bit input Lut that you provides one output one bit output and it can implement M any three input function as you know so this uh stuff I think is already uh familiar for you from the lectures Professor Mutu and then um essentially you can combine these Luts uh in order to this is still three input but how to implement complex function we need FES are composed of many Luts and switches so in the end U yeah yeah this for example is a FJ chip and this a small dot is actually this for example so you have a lot of these and then um you need to basically combine all these Luts to create bigger function for example if you have three input Luts and your function is four input so you can think of how many three input Lut you need to use in order to make a four input function think about it but yeah so modern AIA architecture they typically use Luts with six bit uh so there are six LS and we have thousands of them and we have megabytes of distributed onchip memory that all these onchip memory are essentially used to configure um Luts and also switch boxes so when whenever for example you want to configure this switch box for example here to connect this wire to this wire you need to somehow configure it and there are small memories that you can actually configure each of them using a bit stream and that makes that connection happen essentially so yeah ex exactly this is uh uh for an memory but at the same time for better efficiency F FJ also has some hardcoded special purpose Hardware blocks for example multiplayers are usually very expensive and if you want to implement multiplayers with Luts their performance it might not be good so there might be some as um specializ special purpose Hardware locks for multiplayers and whenever for example you have a multiplayer in your design you just use that for example modern basically fij they might actually have they might have also processor so there might be some microprocessor on on your fbj chip or also beside your micro fbj chip yeah exactly even a general papers processor can be embedded within the FG chip and this is an example of mod fij platforms Z links Inc Ultra skill plus and again this kind of advantage and disadvantage of fij is that you know um essentially as advantages we can say that an algorithm can be implemented directly in hardware and we have high specialization high performance and High Energy Efficiency we have low development cost comp of course compared to custom Hardware design which is AEK for example and we have short time to Market and U use ible and reusable for many purposes so that's why fjs are quite um useful and widely accepted but of course they also have disadvantages so they are not as fast and power efficient as dedicated Hardware customized for an algorithm and reconfigurability comes at a cost significant area and latency overhead as well as I would say reliability overhead as also so uh there are all these switch blocks and you are controlling all these with some memories so if something happen in that memory for example one zero goes to one or the other way around then the whole circuit is just can be wrong right so there are a lot of reliability issues that also can happen in a fij as well as other circuits but that's also one of very important things to know about a fij yes so the latency overhead would you say that it's usually still faster to run I would say usually yes yeah that's usually the case specifically because um on a general purpose procor you have this sequential program so there is this stuff that I mean even though you can also have some parallel programming but still there is a program that there are a lot of sequential instructions that you need to go over them one by one but the PJs are kind of they are assembling Hardware which has a lot of concurrency so that's why in general their performance is much better but at the same time they comes at the cost of uh stuff that I mention and also their performance is not as good as uh AC and custom devices yeah very good question yes but if you already have some sort of for example like some some specific part of the chip that's some yes F of AD no no probably no um yeah usually so yeah I mean that's setting actually the today's systems are actually heterogeneous and they are using general purpose cores they are using gpus in GPS they also have tensor cores kind of customized for that application so actually today's system are comb are combining all these different um basically platform so in in a modern system we have CPUs actually this this this is also as Professor M also mentioned this is it shows apple apple M1 chip which has actually has GP use has also general purpose course FBG maybe not fbj but many other acceler as so basically today system are combining all these and that's why because we need there are not many not every application can be accelerated in either of them so there you you need to benefit from the uh all these thing together essentially yeah any other question okay great so to program an FJ we are using computer AED design or cat tools um fjs have many resources Lut and switches and they are hard to program manually of course so it's going to be very headache if you want to do that so how can we represent a high level functional description of our Hardware circuit using the FJ resources and then we need to select the resources to map our circuit to and then optimally configure the interconnect between the selected resources and generate the final configuration file to properly configure an fpj so if you don't have cat tool we need to do everything manually but luckily we have cat tools that we have this program problem definition and then we use kind of Hardware description language like very log and VL which going to see in a bit um so that's your job or our job but after that we will use cat tools so there is this logic synthesize that synthesize your very L programming essentially to Logics and then there is this placement and routing to place your Logics on all these fpj uh configuration blocks and then how to rot them uh by configuring all these switch box and then uh after placement and rting we will get to this B stream generation that essentially um that b stream needs to flow to your FJ and configure every single uh Luts and memory that you have on your FJ so after happening after this P stream generation and that communication you're going to have your circuit on your Fiji essentially that is automated luckily fortunately uh with different tools but in this course we're going to use Z links V tools so VI is a software tool that help us through out a FJ design flow and this provide tools uh provides tools to simulate also our design to validate the correctness of the implementation debugging and many other things also V also provide drivers and graphical interface to easily program they future using a USB cable and it's this application already installed in computer rooms uh in our lab rooms essentially so you can also check uh basically tutorial of this vivado using this um basically video I'm not going to play it now so you can play it at home apparently I'm supposed to play it but yeah I would skip it okay so keep in mind that you do not need to install V on your laptop I mean you can do it if you want but lab PCS already have it installed and please do not ask T to creade your Labs outside of lab hours and submit your lab files in the correct format so the format is already specified in your in your your lab manuals and please double check your uploaded files and do not incorrectly submit you know because that can cause uh zero points for you and double check your grades essentially so when we want to finalize your grade we will we will send an email to remind you but very important that you check your lab grades back by then and tell us let us know if something is missing and then we can fix that problem in time hopefully okay so that brings me to the end of uh this lecture but I want to also talk a bit start at least very Lu very quickly um just to give you you some food for thought and then we're going to continue very Lu next week we have 12 minutes um of course we cannot cover the whole this lecture but we're going to see a little bit about this so yeah this is the agenda for not today much but yeah anyway uh we will basically we're going to get to we want to get to this processor um next week uh and the weeks I guess after how to design a processor but now let's also quickly talk about Harare description language and very like first I want to use uh some pictures to motivate why we need that so this is a a chip in 2017 which was one of the strongest ship back then and it had U 1.75 billion transistors so people were kind of kind of you know what we going to do when we have billions of transistors and nowadays actually we are way away um you know from that so in uh about 47 years uh We have basically one millionfold gross uh in transistor count and performance this also another chip in 2021 which has 16 billion transistors this chip is in apple M1 Ultra in 2022 that has 114 billion transistors which you can see that it's growing and growing so of course it's not easy to configure every single transistor you know by our own so that's why we need some you know tools for that there's also SOS in 2019 that has 1.2 trillion transistors and largest GPU back then had 21.1 billion transistors and another version of cus wave scale agent two has 2.6 trillion transistors and also the we also check what Wikipedia says about it and as expected uh memories are actually having way more transistors so like flash memory in 2022 has 5.3 trillion transistors or for example um yeah gpus in 2022 has had 18 billion transistor so you can actually see that uh here is also very important so the dram includes about um 12 quad quadrum yeah thousand of um basically um Trum transistor and that's about 97% of the whole uh of the old transistors so that shows actually that most of our systems transistor are actually spending on memories so make sure that you always memorize that that basically memories are actually very very expensive in terms of number of transistors okay so how to deal with this complexity we are using Hardware description languages and what we need for Hardware design that provides ability to describe and specify complex designs and to simulate their behavior functional timing and to synthesize using automatically designed as as we showed like uh vivalo as a cat tool basically so Hardware description languages enable all the above and um they are designed for um basically describe hardware and we have different version of it they they call as hdls but very like vhdl are the most common hdls people actually both of them are um useful but in this course we're going to learn about very luck and of course if you learn one it's not hard to learn the another one okay so as I said there are two wellknown um HDs very lck and vhl here we provide some history about it that you are you can check if you're interested but that's not the most exciting thing that we can bring from this course okay so why specialized languages for Hardware so hdls enable easy description of Hardware structures um so specifically you can also you can think of using why not using for example C programming you know uh to specify Hardwares the reason is that I mean hdls are customized for hardware and in Hardwares we have some uh basically components like we have wires Gates registers flip flops clock Rising falling Edge and all these uh basically components or specification that they are not necessarily provided in sequential programming like the C++ for example so that's one reason another reason also is to enable basically paralleles so in Hardware we have a lot of concurrency so every single actually all these transistors all Gates they are actually operating in parallel so there is no sequential uh thing happening in your design so that's why actually uh if you want to model your Hardware using for example C program or using python it's going to be very hey because it's very hard to um simulate that parallelism and that's why actually why our simulators that people develop for example Simulator for GPU using C++ these simulators are very hard to design and also they are really slow because so they need to actually simulate all this complexity and all this uh concurrency that we have in the hardware which is not the easy thing to do so htls enable that and all all Hardware Logics can operate concurrently in htls and both of the above is U specification simulation and synthesis uh for your Hardware so htls basically we have some key design principle that we should consider we have this hierarchical design that we always need to design a hierarchy of modules uh for our system so in in a complex circuit you actually have you can see that there are many blocks but each block actually can be cons can be basically structured by many many gates so we def we use some predefined we call them primitive Gates like and and or these are actually some kind of leaves in your uh hierarchical design that you don't need to go below yes yes yeah um and simple modules are built by instantiating these Gates like components like multiplexer so we're going to see more about it later so basically you need to make a hierarchy of your design so you can have a top down approach that we're going to see in a bit or bottom up approach uh to design your big system so top down approach you have a top level modu which for example your top level module is a let's say microprocessor but then you're going to see okay my microprocessor can uh would have some subm modules and then you need to design each of these sub modules but each subm module also can have some sub modules and then you're going to get to some leaves and these leaves are actually your Primitives the one that you don't want to go below of that for example in very L you can say that okay my gates are those leaves you may design you may combine some gates and make some bigger Logics like for example adders multiplayers and then you may consider adders or multiplayers all these are metic units as your leaves essentially but anyway there there should be there going to be some instance that you don't want to go below of that and this the kind of top level methodology that you might have you can also think of bottom up design methodology that you first identify the building blocks that are available to you to you or to us and then we build bigger modules using these building blocks and these modules are then used for higher level modules until we build the top level module in the design so so you can also go the way around and I should acknowledge that in our system so when as a designer whenever you want to design system you actually need to use combinational BS so you need to have kind of top- down approach first because you should should be motivated to what you want to get but then um when you want to implement you usually use the bottom of approach so you you design your I mean you make the this hierarchy using top down approach but from the implementation why usually go bottom so in order to define a module in verilog so module is the main building block in verock um that's a notation we first need to define the name of that module and directions of its ports like input and output so this is an example module that we have and it has three inputs a b c and output Y and then we want to describe the functionality of this module essentially so this is the example very L code for that you start with Define definition of the module you say these are keywords essentially module and then the name of modu which is example and then you have these Port lists a b c and Y these are ports and then basically you need to Define which which of them is input which of them is output so here for example a b c are inputs and why is your output and then basically this part you need to specify the functionality of that maure and in the end you have this end module which close your block and also you can also have different style uh so this two definition both are correct so here you say that module for example test a y and then you say input a input B output y you can also say module test input a input B and output y so both are correct and it depends on your style the way that you want to write so what if if we have multi-bit input and output we we can all use Define uh using this kind of range so you put range end and range start and that uh shows the number of Beats you have so number of Beats is actually range end mind the range start plus one example so for example here you have input 31 to0 a that means that actually a is actually a value uh which is 32 beat and then you can specify every single of Beats of a using this this notation a31 a30 a0 and so on so forth you can also do for example this B1 you don't need to put zero always you can say that for example output 15 to 8 B1 and this basically B1 has 15 until B18 essentially this is also another example 7 to Zer and you can see and you can also have this input C which is single bit signal so here when you say 31 to Z actually it represents a 30 32bit value so we prefer actually to Define it as is but you can always you can also Define it as 0o to 31 a but that's uh that's not very common to use when you want to design Define a multi-bit value you usually use this kind of notation 0 to 31 when you want to resemble kind of array definition so you have the array and you want to Define every bit of it okay so and it's also good to be consistent with our representation multi-bit signals always we can use this kind of um notation and for whenever you want to design Define an array you use this kind of notation okay I think it's a good place to stop uh we will continue very luck next week have a nice weekend