Lecture Notes: Von Neumann Architecture

Introduction to Early Computing Machines

• Early computers had fixed programs.
  • Example: Desktop calculator - fixed-purpose for mathematics.
  • Changing programs required rewiring or redesigning.
• Stored Program Computer: Allows changeable programs.

Von Neumann Architecture

• Introduced by John von Neumann in 1945.
• Key Characteristics:
  • Central Processing Unit (CPU) with a single control unit.
  • Arithmetic Logic Unit (ALU) within the CPU.
  • Onboard Cache: High-speed memory for instruction/data control.
  • Internal Clock: Synchronizes components at a constant pulse.
• Process: Fetch, Decode, Execute Instructions.

Program and Memory

• Programs consist of a sequence of instructions stored in main memory.
• Instructions are fetched to registers within the CPU for processing.
• Memory Addressing:
  • Each memory location has an address.
  • Processor fetches instructions by address.

Special Purpose Registers

• Program Counter (PC):
  • Holds memory address of next instruction.
  • Incremented after fetching an instruction.
• Memory Address Register (MAR):
  • Holds address for data to be fetched/stored.
• Memory Data Register (MDR):
  • Holds data fetched from or to be written to memory.
• Accumulator:
  • Holds results of calculations from ALU.

Fetch-Execute Cycle

1. Fetch Stage:
   • PC is checked for the next instruction address.
   • MAR fetches the instruction into MDR.
   • PC is incremented.
2. Decode Stage:
   • Instruction copied into cache.
   • Control unit decodes the instruction.
3. Execute Stage:
   • If needed, fetch more data or perform operations.
   • ALU performs calculations, results stored in Accumulator.
   • Results can be written back to RAM.

Recap: Von Neumann Architecture

• Components: Control Unit, ALU, Memory Units, I/O.
• Stored Program Concept: Instructions and data stored in binary form.
• Registers: Small, fast memory within CPU with specific functions.

Detailed Fetch-Execute Cycle Example

• First Cycle:
  • Fetches instruction from address 1.
  • LOAD instruction decoded, loads content from memory address 5 to Accumulator.
• Second Cycle:
  • Fetches instruction from address 2.
  • ADD instruction decoded, adds memory address 6 content to Accumulator.
• Third Cycle:
  • STORE instruction decoded, writes Accumulator content to memory address 6.
• Fourth Cycle:
  • End instruction decoded, terminates program.

Conclusion

• Example program calculated and stored the sum 12 + 23 = 35 in memory.
• Understanding the Fetch-Execute cycle demonstrates data/instruction movement in the CPU.
• Registers and cache optimize data retrieval and processing speed.