COMMS 10015 Computer Architecture - Week 5 Lecture 4

Overview

• Focus on ARM v7-A instruction set architecture (ISA)
• ARM v7-A represents a general-purpose profile, suitable for applications such as operating systems on mobile phones or laptops.
• ARM v7-A is a RISC-like, 32-bit load/store architecture.
• Implemented in microarchitectures like ARM Cortex-A7 (used in Raspberry Pi).

ARM v7-A Architecture

General-Purpose Register File

• 16 general-purpose registers, addressed using a 4-bit index (R0 to R15).
• Human-readable identifiers (e.g., A1 to A4) also used.
• Register 15 is the program counter, can be used as any other register.

Special-Purpose Registers

• CPSR (Current Program Status Register)
  • Controls execution; reading gives execution status.
  • Key Bits:
    • Bits 0-4: Processor mode (affects privilege levels).
    • Bits 28-31: Flags N, Z, C, and V (comparison results).
• SPSR (Saved Program Status Register)
• Use MRS and MSR instructions for CPSR/SPSR.

Memory Model

• Byte-addressable with a 4 GB address space.
• Alignment Rules: Instructions aligned to 4-byte boundaries.
• Endianness: Little-endian by default; data access can be little or big-endian.

Instruction Specification

Instruction Encoding

• Fixed-length, 32-bit encoding.
• Multiple instruction formats, some complex.
• Three-Address Format: Standard, allows three register operands.

Instruction Classes

Data Processing

• Arithmetic operations (e.g., ADD, ADDS to update CPSR flags).
• Flexible second operand (immediate, register, shifted/rotated register).

Data Movement

• Immediate/Direct Moves: Move immediate or register values.
• Single & Multi-shot Memory Accesses: Load/Store multiple registers.
• Stack Operations: Push/Pop using stack pointer.
• Addressing Modes: Indexed and scaled indexed.

Control Flow Management

• Branch Instructions: B and BL, with immediate/computed variants.
• Program counter as part of general registers allows extended computed branches.
• Predicated Execution: Every instruction has a conditional execution based on predicates.

Execution Optimization

• Predicated Execution: Efficient control flow manipulation, reducing instruction count and execution cycles.
• Example: Optimizing a GCD function using predicates to minimize branches.

Conclusion

• ARM v7-A bridges theory and real-world application of instruction set architectures.
• Supports understanding of how real computers work, visible in practical study and devices in everyday use.