Transcript for:
Understanding CMOS Inverters in Circuits

hello everyone so now we will study the concept of CMOS inverter so many people who prepare for analog domain specifically they ignore this stuff we can say that it is asked in digital entry only but no even for the analog inputs you can Analyze This circuit right it is basically a circuitry and it it has also a high gain we will see the gain of it so it has also a high gain so this is used in analog uh in analog industry okay so CMOS inverter is important topic okay so now first you will see what is a buffer and what is an inverter so what is the main difference between those two so basic difference we will see let us assume this is a buffer okay this is how we make a buffer so this is how we make a buffer so in case of buffer if you give a high high input you will get a high output okay and in case of buffer if you give a low input you will get a low output this is what a buffer is okay I'm talking about a inverter so this is how you make an inverter okay yeah so in case of inverter high output we get if we give high input we get low output and if we give low input we get high output this is the case of inverter okay so now we will see CMOS inverter so first we will analyze the CMOS inverter for pulse input okay so what is the circuitry of CMOS inverter that we will see this is the pmos and then in series with the nmos okay so this is the circuitry and both have a common input okay both have a common input V in and this is vdd from drain of nmos and from drain of pmos we get the output okay so this is the circuitry of CMOS inverter and what will happen if we if we interchange the pmos and nmos it will become a buffer I will upload that video okay no problem I will upload that video if we interchange it what will happen that we will upload okay now the input is pulse right so we will make a we will make a pulse input okay so like this is time 0 this is T by 2 this is T this is 3 T by 2 this is 2T and one thing is that P is very large that would be given okay T is very large um and one input what we can put is 0 volt one input we can put a zero volt and one we can put is vdt okay so we will analyze it now for analyzing I will use it so four zero to T by 2 4 times 0 to 2 by 2 what is your v e v is equals to zero then we in case of pmos in case of pmos if you see here vsg would be vdd right and in K in case of output we can connect a capacitor okay here in the output we have some load that is a capacitor okay so that we have connected so what is vsd vsd vdd and what is your vsd that is equals to VD as well because your drain is at zero potential vsd is at VD only initially at T equals to zero at T equals to zero okay so here this vsg is greater than vtp right vdd like the value is not given but you can take okay let vdd equals to five volt v t n equals to mod of vtp equals to 1 volt okay so vsd is greater than mod of vtp that means it is on and in saturation region why in saturation region because vhd is greater than vdd minus vtp right vsd is greater than vsd minus V T then it is on and in saturation and in case of nmos at T equals to 0 in case of nmos at T equals to zero vgs would be 0 only that means it is o is on nmos is off so four zero to T by 2 your pmos is on and your animals is oh so if you draw the character six now what we can write is initially pmos is in saturation region okay so what happens is that pmos can be replaced with current source right pmos can be replaced with that current source and nmos will be open circuited this will be open circuited so now what is the situation is that whenever it is whenever a device is on whenever a mosfet is on and it is in saturation region it will be replaced with the current source and whenever it is in a linear region it will be replaced with the our own resistance right our resistance right we know that right our own resistance okay so now this is replaced with the current source and at output we have this capacitor C right this is V node this is the capacitor C and this is open circuited right this pmo this is pmos and this is your nmos right and this is vdt now whatever the value of this current source is that will charge this capacitor and the capacitor will start charging the capacitor will start charging linearly okay so the capacitor will start charging linearly initially it will charge linearly okay so this is your V node versus time T curve now it will charge it will charge now at one point V naught will reach one volt right and this is five volt in this case your vsg is fixed your vsd is fixed at five volt right your vsg is fixed at fivefold and your vo Drive is vsd minus VT it means four volt now your V node is getting up that means your vhd is getting low if your V naught is getting up your vhd is getting low when V naught equals to 1 volt when V naught equals to VT or when V naught equals to one volt your vhd would be equals to 4 volt right where vhd would be equals to forward so after that it will go into the saturation region now now V naught is increasing that means your vsd is decreasing but V overdrive equals to vsg minus v t p that is equals to 4 volt is fixed that means and pmos is moving towards what moving towards linear region right linear region okay your V node is increasing that means your vsd is decreasing that means your and your vo Drive is fixed that means if it is moving towards the linear region okay so it is moving towards the linear region so when we so at point of no at vsd equals to vsg minus mode of vtp okay so what is your vsd vsd is vdd minus V naught your vsd minus V T is 4 volt so we reduce 5 volts so V naught would be equals to 1 volt Okay so when V naught is greater than one volt at that time your vsd is less than vsg minus vtp that means at that time linear region we are moving towards the linear region and if we are moving towards that linear region that means pmos will be replaced with replaced with our own right so this will be replaced with some our own value and this is vdd and no comments about pmo nmos because it is still off right so this is V node and this is like this right here I can write and most is still off and most is still off okay so now it will charge exponentially so exponential charging is there okay so instead of making this curve here I should have made it on next page but forget that we have written the explanation so after this it will charge exponentially so I can make it look like this and till what voltage it will charge it will charge till vdd voltage right from 0 to bdd it will charge and this is what is we don't know the value of time but we know that this is the value VT right when whenever when V node is equals to VT over 1 volt here we have seen after that we are going to the linear region so this is the linear region and this was the saturation region right so you understood this but in many of the book or in when you even in the interview if you say that the pmos is on so it will be replaced with the resistance so we will see exponential charging Factor so even that would be that they will also consider if we see it deeply we see that initially it is linear linearly chart after that it is exponentially charged okay so but in the interview they don't notice this much if you say that it is charged exponentially then they also considered it so this is what is happening for for a very small region it is in saturation region then it goes to linear region now everything now for for what 4 T by 2 2 time t your v in is 5 volt right or t by 2 2 time T your v in is vdd that means VN is 5 volt so now for pmos 4 pmos your vsg is 0 volt that means it is right so pmos is off and for nmos or nmos what is your vgs that would be five volt what is your V Overdrive View Drive is 4 volts vs demand and what is your V d s that is equals to V naught okay and currently at T equals to 0 at T equals to 0 your v d s is V node that is equals to five volt right because it has been charged till 5 volt it has been charged till 5 volt right so at T equals to 0 so at T equals to 0 yo VDS is greater than V overdrive that means it goes to saturation region okay so nmos will be replaced with current source right so your nmos will be replaced with the current source so this is the pmos that is open circuited this was vtd okay now this is the capacitor there okay this is V node and this is the current Source right this was already charged to vdd that means five foot now the current is flowing in this direction so this discharges the capacitor linearly that means here V node goes down okay so your V node goes down so that means VDS for nmos goal down if it is goes down that means nmos is moving towards what linear region that means when vsd is less than V overdrive so what is vsd that is V naught that is less than 4 volts then we will move to linear region right so how will the output look like what I can do is that I can simply copy this one and I will paste it here so first what is happening is that it is linearly coming down right so from 5 to from v d to from vdd2 it comes down to vdd minus VT right we did E minus V T and then if it has moves to linear region then nmos will be replaced with R1 right so there will be exponential discharging this is charge to 4 volt this is replaced with r on okay and this is open circuited and this is v d d okay so this will get discharged from 4 to 0 we will go but exponentially this time so this is how it goes to 0. and now the same cycle goes on okay okay this is time T then again the same cycle repeats again charges then linear then this is in the saturation and then it comes to the linear region okay so this same cycle goes on so from these two this we have this is the saturation region and this is the linear region okay so this is the complete analysis but in the interview if you say it has exponentially charged and it will get exponentially this charge then they can somehow consider it but if you tell this first it will be in saturation then it equals to linear region then it comes down so this is the exact analysis and this is the correct analysis okay so so now you have understood this concept and there can be few more questions okay so what they can do is that I will add on this vision so what they can do is that they will make the same CMOS inverter this is v in vdd this is also V okay I am just making it separately nothing else this is your V out this is grounded now what I have done is that I have connected one more and more in parallel okay you know what does design mean right I have told you in one of the video I guess okay what does this sign mean the same potential we this sign really means like this okay the same potential VN is applied there so we can make it like this as well to make the Circuit look less complex we make make it like this so This Vin is applied here as well okay so this is what it means and now this is the capacitor C so now you need to comment on capacitor charging and discharging come on capacitor speed of charging and discharging so tell me the speed of charging and discharging how it will change first we talk about the speed of charging when the capacity is charging that means your pmos is on your pmo season so there is only one pmos so there is no change in the speed of charging speed of charging Remains the Same now coming to the speed of discharging so in case of 1 pm and most we have two nmos now if we have two nmos so in saturation region we will have two current Source if we have two current source that means we will have more current so more current will be coming out of this capacitor right in saturation region we will have two two current source that means more current will be coming out of this capacitor that means it will discharge fastly so the speed of this charging is increasing or what you can see in case of uh nmos when it is in Triad region it will be replaced with the iron value right this will be replaced with R1 this will be replaced at R1 so what will be the time constant time question would be R1 by 2 into C your time constant is decreasing that means speed of charging is increasing time constant means whatever time it takes to reach some value right whatever the time it takes to see let us assume what is three to time or four to time in photo time the capacitor completely discharge okay so if it is taking photo time that means it will take 2 into our own C time and before it was taking 4 into our own C time right so that's time taken to get the strategies less that means your speed of discharging has increased okay so would be equals to r 1 by 2 into C or discharging that means speed of discharging as increased okay so these kind of questions can be asked okay so this is the complete analysis of pulse input now we will see the most important one that is the that is what that is the ramp input we will increase the value from 0 to vdd we will increase the value of v in for VN of 0 to we will not directly jump from V 0 to vdt we will increase it linearly from 0 to V T and vtn to vdd by 2 from v d d by 2 to vdd minus vtp and then to vdd okay so just just you just need to have a strong concentration for that okay so we'll start it in next video okay thank you hello everyone now we will see a very important topic that is CMOS inverter with ramp input okay so this is the input we have this is the inverter that we have previously studied so previously we studied about the pulse input now we will study about the ramp input so this is the input we have VD equals to five volt we are taking vtn that means the threshold voltage of nmos vtp that means threshold voltage of pmos that would that is equals to 1 volt and we are increasing beam from 0 to 5 volt so for pattern understanding we are taking the value but when we draw the characteristics like in the previous video as well when I drew the then I drew the characteristics I didn't write the values instead of that I wrote the exact Expressions right so now coming here uh in this one okay so the first thing is that we will take V in to be 0 to vtn okay from 0 to VT and we are taking so when V in is less than vtn or greater than 0. that means here the value is less than vtn less than vtn okay that means your nmos is of is on that means your animals for nmos we can write your vgs is less than vtn that means it is O that means it goes in cut off region right and for pmos what happens is that your v s g is vdd minus v t n we can write okay no VD minus V in okay VD minus V in so it is vtp is one volt so it is surely greater than 4 volt right that means this value is greater than vdd minus vtp vtn that means it is greater than 4 volt okay so it is greater than 4 volts so that means your pmos is on your pmos is on and your nmos is off so now it is on but it will go into saturation region or linear region just take your time and think about it saturation or linear I will give you an hint the current in both of the circuits would be the same right i d s n i ID P I will write an ID and I will write so IDP would be equal to the idn right this is the fact right IDP is would be equal to the idiom the same current is going now if you say that there will be some load connector there so that can have some current load will be very high okay it can't it won't take any current so IDP would be equals to IDM that's why I have connected no load here okay IDP is equal to idn okay that is there so just think about it so what is your answer it will be in linear region why so let's see this is our pmos so this is our vdd this was all V in and this is open circuited right your Atmos is open circuited and this is your V naught value right your in and this is open circuit and this is your pmos okay now the current in pmos is zero ID in P0 because the current in ID because the current in most is zero so the current here should be has to be zero right if the current has to be zero then what fee draw the transfer characteristics foreign versus vsg not vsg ID versus vsd so this is the linear region right this is the linear and this is the saturation region so you know that current can never go to zero in saturation region so if your current is zero there is no chance that it is in saturation again because in saturation region the current is always greater than zero so what it has to be in linear region okay because of zero current foreign so what did we see here four zero to V in to vtn in this what about your pmos pmos goes in or pmos goes in cut off sorry not cut off we must goes in linear region and your nmos goes in cut off vision right so this is our first point of analysis okay now we now we will move on to the second region now we have increased V into V greater than VT okay V in is greater than VT now and less than VD by two just forget about this vdd by two just V in is increasing now now your VN is increasing from VT so if V in is greater than VT so in case of nmos what you will see what is your vgs what is your vgs that is equals to vgs is equals to V in right in case of nmos in case of Atmos your vgs is equals to V in now that is greater than VT that means it will be whole if it is on tuition saturation over linear okay talking about the pmos you know v s g is vdd minus V in now V T has just increased so that will surely be greater than V I would drive right first it was 4 volts vdd was five minus V in vtp is just increased let us assume VN is 1.1 volt okay VN is 1.1 volt if VN is 1.1 volt so it would be 4 minus 1.1 that means it would be 3 minus 3.9 and v d by 2 would be 2.5 so 5 minus 2.5 that means 2.5 that is greater than not V overdrive that is greater than mode of vtp right so that means it is also one the question is saturation over linear right now both are on and our can write is as 5 minus 2.5 is always greater than one volt I hope you will understand it the maximum value is 2.5 so it will it will certainly be one right so now the question is both for both saturation or linear now both is both around okay so one thing I have told you is that whenever a device turns on that means it will drive a very low current whenever a device turns on it will drive a very low current okay it it won't take a very large current level of a sudden so it will drive a very low current so that means that that means that there is a very less current through the nmos if there is very less control than most that means there will be a very large clamp through the wemos as well so whenever the device just turns on I have told you this fact before as well whenever the device just turns on it draws no device whenever the most just and so on because in the transfer practices we can see that when vsd is just greater than or vgs it just greater than VT there is very slow current right this curve this is very low right or I can make it a bit properly so this is your VT and this is your vgs and this is your ID if it is just greater than VT so there is very low current okay so whenever yeah so whenever the most just and so on it does a very low amount of current and previously your Primos was in linear region your pmos was in linear region so by the previous analysis what I will do I will just replace it with the capacitor with the resistance so this is R1 and this is your vdd and this is your V naught okay and this is some I can't say some current Source initially I will just make pmos a okay this is your v in so if it is drawing a very less current your V naught will ID is very less very less that shows that V naught is nearly equals to VD at V in just greater than VT okay like just initially if your VT if your VN is increasing from VT from 1 to it is going to 1.1 volt at that time ID is very less that means the drop here is very less at our own resistance the drop is very less that means your V naught is nearly equals to vdd so if your V naught is nearly equals to VD that means your VDS is very small vhd is very small so four pmos vsd is very small that means it remains in linear region for nmos what is VDS that is V naught that is nearly nearly equals to vdd that means it is very large right what is vsg sorry vgs vgs is v in okay and what is V overdrive it is v in minus v t so it is very low right because we need just greater than VT because V in is just greater then VT okay at I should write at V in just greater than VT okay at V in just greater than VT okay so ID is very less and we just get the nvt so V naught is nearly equals to v d that means you your v d s is greater than V Overdrive so that means what it goes in saturation region okay did you understand it right so for z v t n or VT vtn I am writing because vtn is a positive value itself if I if I if I write mode of vtp that will also be fine for vtn to vdd by 2. your pmos is in linear region and your nmos is in saturation region okay so I hope all this is clear to you I will just repeat both of them both of the conditions once initially what we saw is that your VN is 0 to vtn that means your there has to be zero current but in the saturation region what we do we see is that they they can't be zero current so it has to be in linear region so your Primos is in linear region and animals is in cut off region when we increase veeam to some extent from VT if when is increased from VT that means your nose turns on and also your pmos is also on so if you if if your nmos just turns on that means it will drive a very local if it is driving a very low current that means your uh pmos will also drive a very low current now since Primos was in linear region before we will try analyzing it by uh by replacing the pmos with the resistance that is our own so if you replace the pmos with the resistance r on then we saw that since there is very less current so the at pmos there will be very less stroke so your V node will nearly be equal to vdt so for v in just greater than in VT your V naught is nearly equals to vdd so if that is nearly equals to v d then your vhd is very small so for pmos your vhd is very small so if vsd is very small that means it remains in the linear region because if vhd is small it remains with the relay region because we know the characteristics right here we know that characteristic if vhd is small that means it remains in the linear region and in case of nmos what is happening is that your VDS is equals to almost vdd and your V overdrive will just greater than zero right because we are v v over time is V minus VT that is just greater than zero that means it is very low so your VDS is very very greater than vo drive right your VDS is very very greater than V over right that means it moves to saturation region okay so so from vtn so from vtn to vdd by 2 your pmos events in linear region and your Atmos events in saturation region okay so now what is happening is that now your veeam is increasing right your win is increasing right we are increasing V in from VT vtn let us assume from 1 to 1.1 to 1.2 1.3 1.4 right we are increasing V in that means v g I will write vgs n is increasing right if it is in saturation region and moves in saturation region no it doesn't apply and most in saturation region your vgs is increasing if your vgs is increasing here I should write and most in saturation in saturation if your videos is increasing what is the current in saturation region i d equals to some K N Dash v g s minus VT whole square if this value is increasing that means your current is increasing right current ID n is increasing right if your current is increasing that means current in pmos is also increasing because both are in both are connected in series so the current there also should increase that means your ID P increases okay your IDP increases so there there is this current is increasing now what is IDP IDP this is in linear region right till now it is in linear region so it will be some k n k n y k n we can write it and AP it will be some KP into v g vsg vsg minus V T into vsd minus v s t whole Square by 2 right this is the value right now in this one what do you see vsd is fixed right just see here vsd is vdd minus v e not not fixed if VN is increasing your vdd minus VN will decrease your vsd will decrease Vin is increasing so your vsd will decrease because this is weak and this is increasing so your BHD will decrease that means your vsg is decreasing why so because vsg is vdd minus V in since VN is increasing your VN is increasing that means vsg is decreasing but your current is increasing right here we saw that the current in Atmos is increasing that means the current in Primos has to increase as well but your vsg is decreasing so both has to increase if this has to increase so what value has to increase vhd has to increase height because this is in deep linear region just ignore this Factor okay just just ignore vhd Square by two just think about this this Factor okay because vhd is very small so we can ignore this Factor so if vsg is decreasing but ID is increasing but ID in P is increasing that means your vsd as to increase if your BHD has to increase that means your V node goes low right your V naught starts going low vsd p I will readjust these Pages later on so if v s d p is increasing that means your pmos is moving towards saturation right if your vhdp is increasing that means your pmos is moving towards the saturation region right because it's vhd vsd is more than vsd minus VT that means it is in saturation here at some point both pmos and most will be in saturation region look this nmos is already in saturation region and most is already in saturation area so if we are increasing being the current in Atmos is increasing but the current in pmos has to increase as well the current in pmos has to increase as well but in pmos what do we see if we are increasing V in your vsd is getting released if your vsd is getting decreased then there has to be something that has to increase and that value has to be vsd so if vsd is increasing that means the first thing you can see is that the V node is going low okay and the second thing you can see is that if vsd is increasing that means it is moving towards the saturation region so Atmos is already in saturation region and your pmos is moving towards the saturation region so there will be one point where both of them will be in saturation region and the current is already same so your ID in pmos at saturation region would be equals to your ID in nmos at saturation region so let's put both of them equal so mu n mu p c o x W by L let us call this complete Factor as k n k p okay if we are but there is one thing we are doing wrong here is that if we are saying this is at K this is as KP so I should write 2 KP here okay the KP Is mu and c x w by n B mu p c u x w by 2L is KP okay mu p c x w by 12 is KP foreign into v s g minus vtp mode whole Square would be equals to k n V g s oh and this should be vgsp n minus v t n whole Square this derivation is very this division is asked many times so what is vsdp that you should just keep in mind what is vs GP that is vdd minus V in minus mod of vtp KN by k p under root right we are taking under root on both sides into v g s v in what is vgs for nmos vgs for nmos it is v e into VT n right so talking about what do we need to find we need to find the value of v in so what we are doing is that we are finding the value of v in at which we get both of them in saturation region if both of them are in saturation region so the current in both of them are same so this should be these two equations should be the same in saturation region the current will the current in both pmos and nms are always same okay and if both of them are in saturation region we can put those current equals to zero so from here we can get the value of v in so what we are seeing is that v in minus vtp Plus root knkp into vtn would be equals to root KN k p V in right V in or b i we can we should write if we are writing v i here so this is the value yeah so V I would be equals to vdd minus mode of vtp Plus root KN by k p into vtn upon there is something wrong I guess we need wean will come here as well right this VM will come here as well so a phone 1 plus root KP knkp one plus root kn p so this is the final expression right okay if mod of vtp is equals to vtn and t n equals to KP then your v in would be this is equal to k n equals to KP which will this will get canceled so and vtp and vtn are equal so this will also cancel this will become one so your V would become vdd by two so so this would be the switching threshold okay we will talk about this point what is switching third load at this point both and most and pmos your both and most and bmos are in saturation region okay so this we have seen is that there is one necessary condition is this k n equals to k p equals to vdd by 2 both pmos and nmos goes in saturation only when KP is equals to k n right that means your mu n C of x w by L ratio of k n equals to kpi will write because I have written for k n equals to KP then c x w by L ratio of n would be equals to Mu P Co x w by L ratio of P that means your mu n w by L ratio W by L ratio of P upon W by L ratio of n is equals to Mu n by mu p okay so this is one more important factor so generally generally I guess most of you knows that generally the mobility of electron is more than the mobility of holes um million is greater than mu P the mobility of electron is more than the mobility of holes a rough idea is Mu n is almost equals to 2.5 of mu p okay that shows that W by L of pmos should be equals to 2.5 of w by L of n okay that means pimos if we want saturation region at V in equals to vdd by 2 then W by L of P should be greater than W by L of n and the rough margin is w i l of p q nearly be equals to 2.5 of w by hello n that's why the size of pmos is larger than that's why the size of pmos is larger than size of nmos in CMOS inverter okay so this question is asked many times like why is the size of pmos is greater than the size of animals okay now they can ask you more things like that if you if you can write this expression if you can remember you should remember this expression as well okay so if you can write this expression they will ask you how you will change the value of v in where this point is called switching threshold okay why it is called switching threshold we will see so how can how can you change the point of switching threshold okay so how can you change by changing the value of k n and KP okay so this this Vision are all stretchable okay and they can ask you more questions like that if uh if KN is four times of KP then what will happen to the switching threshold okay if k n is 4 times of KP then just write put down the value here assume vtp equals to vtn then your scan is four times okay then your we did it later let us take video equals to five volt so it would become 5 plus 2 upon 1 plus 2 so it would be 7 by 3 and 7 by 3 is lesser than 2.5 so your switching threshold will decrease and they can take a other condition as well okay if KP is four times of that then what will happen five plus one by two five point five upon uh one point five five point five five upon 1.5 what is that that is greater than that is greater than that is greater than 2.5 that means your switching threshold value will increase so that's how you can change the value of switching threshold by varying the value of k n and KP okay so these questions are these questions are very very much charged okay so you should uh know this concept both are moving to our saturation and and at that point we just put the value equals to both of the value equal then we got this VM value okay and then we just uh took this scenario because uh we are taking k n equals to KP that means your VN is uh thresh V is uh uh Vin is at saturation add both of the animals and pmos are are at saturation when VN is equals to vdd by 2 okay so this is the condition that we are taking so we can write when V in is equals to vdd by 2 now we will write it later on so since pmos is in saturation region okay and and most is also in saturation region okay so for pmos what is vsd vsd what is vsd for pmos vdd minus mode of minus V in and what is V overdrive that is vsg minus mode of v t this is vhd minus V naught actually vhd is v d d minus Vietnam and that is vsg minus vtp and what is vsg vdd minus V in minus mode of vtp at saturation at saturation what is happening vsd is equal to V overdrive right so vdd minus V naught is equals to at saturation what is the value of v it is vdt by 2 right so it is VD by 2 minus mode of vtp from here what is the value of V naught is coming that I need to write so where I should write it I will just shift it upwards okay so here your V naught value is coming to be vdd by 2 plus mod of vtp right so we know the mean value so since v n equals to vdd by 2 we have saturation region so just we put V in equals to v d by 2 here and just thought and just go to know what is the value of V naught that is v d by 2 plus vtp and in case of nmos VDS is what is VDS that is V node what is V Overdrive V overdrive is what is V out drive vgs minus VT vgs is V in minus v t p and at saturation VDS would be equals to V in minus v t b v n is vdd by 2 minus vtp okay so this is the condition here and this is the condition here now add so at V in equals to vdd by 2 VR getting two outputs V naught equals to vdd vdd by 2 plus vtp and V naught equals to vdd by 2 minus vtn so what would be the value of output both of them will be there so how will the curve look like so for this much characteristics we will draw the curve now okay or this much value so how it started initially it was at V out was at vdd right talking about V out versus V in so till this point this was V T and we can say so did we discuss the value of V naught here we we should have described the value of V naught because if this is if it if this is just off right if this is of sorry if this is in linear region and this is off okay it is on and it is in saturation so it is in saturation region so there is no current across it so there is no current across the register so V naught is equals to VD only V naught is equals to VD only because we can replace this with the resistance so V naught is equals to vdt if we replace that with the resistance our own so there is no ground across that resistance so V naught is equals to vdd right so V naught is equals to VD here so we should have written it here V naught equals to vdd right and in the second case what we have seen is that in the second case if we are increasing the value of v v in from vtn your V naught goes down that means your V naught goes down right so your V naught is starting to go down so after that you V naught is starting to go down now at vdd by 2 what is happening by 2 what is happening try it in the middle note this this so if this was vdd okay after that it was decreasing so at vdd by 2 there is some point this is that point and this is that point so at some point we have this is the Middle Point here we have V naught value equals to VD by 2. at this point we have value equals to vdd Plus mod of vtp how it came VD by 2 that I will tell you and at this point we have vdd v d d by 2 plus vtp and here we have vdd by 2 minus v t n we just took the average take average so V naught average would be we did both addition by two so it would be VD by two so basically at V naught equals to v d by 2 what is happening is that we have output equals to vdd by 2 plus VDP as well and output equals to vdd VD by 2 minus vtn as well okay so this kind of output we have and also the average Z value will be there so whenever they ask what is the output at v v equals to VD by 2 we will say VD by 2 okay just the average we will say so the curve is looking something like this now it will go like this so the nature occur ahead we will see so now the analysis will be very easy for you why because you have seen everything related to related to this now analysis would be easy for you so the third one is now the next condition is are we putting the numbers no we are not putting the numbers so now you win is greater than v d d by 2 your v in is greater than we did by 2 but lesser than bdd minus model VT P I am not going to the inverter circuit again and again but I hope you are understanding it okay I think we don't need to draw the circuit again and again okay for this one because it is too long I guess I should treat now we can take it right so now your VIN is basically greater than 2.5 volt and less than 4 volts right so if it is less than 4 volts this will be on because 5 minus 4 will be greater than 1 5 minus 3.9 it will be greater than 1 so your here your pmos is on and also your nmos that means it if it is less than 4 if it is greater than 0.7 it will be only so it is less than four so your animals is also right so again that equation region what is the region and what is the region of operation right so for Primos we can see here we can write the region of operation as well so I will put this vdd here so here your pmos was in linear region and your nmos was in cutoff region here your pmos was in linear region and your nose version saturation region here your foreign okay now we will talk ahead so for pmos you will try writing vsd what is vsd with D minus V naught okay what is v s g minus V T that is equals to vdd minus V in by 2 minus VT right let us take V in equals to 3 volt okay so 5 minus 5 minus 3 by 2 minus 1.5 minus 1. so it would be 2.5 okay and vsd would be 3 5 minus some V naught V naught would be lesser than 2.5 only right because V naughty decreasing only we note it decreasing why so if V in is increasing that means the current here is increasing if the current here is increasing that means the current hair also increases but here vhd is decreasing so if vsd is decreasing then vsd has to increase so if vsd is increasing if vhd is increasing that means the pmos is moving towards saturation and the value of V naught is decreasing the same concept that I have explained before or there is one more way to analyze it that we will also see first thing what I am saying is that when is increasing idea is increasing idea is increasing that means your IDP is increasing if IDP is increasing that means one factor has to increase but vsg is decreasing if vsg is decreasing then vsd has to increase vsd has to increase so if vsd is increasing that means it is moving towards saturation so your pmos is in saturation region Primo season saturation region okay now your V naught is decreasing your V naught is decreasing that means your VD VDS of n is going low talking about nmos if we talk about nmos V naught goes low that means your v d s of n goes low that means it moves towards what linear region right so that shows that your nmos is in linear region now basically it's an inverter okay if you have seen the connectivity till now P was in linear and was in cut off P was in linear and was in saturation though both in situation now what will happen n will go to linear we will go to saturation inverted okay and we'll go to linear and P will go to saturation okay and simply by uh concept as well you can see right the current is increasing V vsd has to increase and if vsd has to increase that means we V node has to go and go low and if vhd is increasing that means it is pmos goes to saturation and if V node goes low that means your nmos goes to linear region okay so for V in equals to VD by 2 2 V in and vdd minus mode of vtp what is happening your pmos is in saturation region and your nmos is in linear region and your V node goes low right so this is what is happening okay now we will see the last condition what we could do is that we could have seen that we could have seen this condition before as well okay this is the last condition now your vdd minus vtp okay and lesser than vdd okay so now basically your V needs between 4 to 5 volt right see this here if we have 4 volts and here if we have something greater than four volt let me let us assume 4.1 volt so your pmos will be off and your nmos will be on will be off right at 4.1 it will be o so pmos will be of and your Atmos will be over now what will be the reason of operation tell me linear right because the current is zero ID n equals to 0 is possible only in linear region right so for this condition vdd minus mode of vtp to V in less than vtp vdd the at that your pmos goes in Cut Off and your nmos goes to and most goes to linear region okay and what will have what will what will happen to V naught value V naught nearly goes to zero why so because this will be replaced with the resistance right and there is no current in that resistance so V naught goes to zero one did you understand it this will be replaced with the resistance only this will be replaced with the resistance and at this resistance we are nearly having at this resistance we are nearly having zero current so V naught goes to zero only okay so V naught nearly goes to zero okay now we will draw the transfer characteristics complete transfer characteristics so from this curve we can pick it up foreign this is not that state forward analysis okay so now drawing that complete characteristics this point will be vdd by 2 no not bdd by two it's going to be VD by two minus mod of vtp okay then it goes down to zero so it goes down like this then it goes down to same kind of curvature we need to make and then it goes down to zero okay okay so in this region your pmos was in saturation and your nmos was in linear region and in this region your pmos was in linear region and your nmos was in cut off Vision okay I hope you have understood the concepts now right and there is one more way of looking at looking at that looking at this this region okay this second region in this region when it was saturation in India so if we try to do the analysis from backward side okay we are trying to do the analysis from backward side so let us assume we are going from 4 volt to just 3.9 volt we are just going from 4 to 3.9 at 4 volts at 4.1 volt it was off now we are going at 3.9 so it just turns on the pmos just turns on that means the current is very low and since this is already in linear region so it will drive a very low current that that means it will have a very less voltage drop if it is having a very less voltage though that means V naught will nearly be equals to zero V node will nearly be equals to zero yeah right look from 4.1 to we are going 3.9 that means the pmos just turns on that means there is very low current and the animals can be replaced with the resistance that means that resistance will have a very less voltage drop that means V naught will nearly be equals to zero volt if V naught is nearly equals to 0 that means your VDS is very low in case of nmos and in case of pmos yeah and he's in case of pmos your VDS is very large so if your VDS in case of pmos your vhd is very large large so in case of pmos if your vhd is very large that means your pmos is moving towards saturation and your Atmos is moving towards linear region so from the previous analysis we can see at 4.1 volt uh and most pmos is of animal season now from from 4.1 we are going to 3.9 so the pmos just runs on if the pmos just turns on less current less current in pmos and less current and most less current inmost that means nmos will have lesser voltage if the nmos is having lesser voltage drop that means lesser voltage of V naught well V node value is less that means V naught is nearly equals to zero that means your VDS for vds4 nmos is very less if your VDS for nmos is very less that means it is in linear region and your vhd for pmos is very large if your vhd for pmos is very large that means it is moving towards the saturation region so this is one more way of analyzing the circuit okay now we have seen the voltage transfer characteristics so this is VTC this is voltage transfer characteristics now we will see current characteristics okay so in the next video we will see just revise it once again whatever I have taught okay not too much straightforward what they will ask you from this they will just ask you the region of operation just tell me the reason of operation that's it that's it they will ask okay and also that knkp thing that I told if k n is greater than KP what will happen the the Curve will move towards the origin if the k n is lesser than KB okay so we can write one thing here is that k n equals to kPa if k n in the formula we saw that if k n is 4 times of KP 2 times of k p and v t n we will see it in next page only okay so I have to draw two more cars so that will be a good question okay we will see it yeah so we derived this condition right what was the value of V for uh for Veen for both pmos and nmos being in saturation here reinforce saturation in both pmos and nmos so at what value of p v it goes to both Atmos and pmos goes to saturation unit so this is what we call switching threshold switching threshold why it is called switching threshold because from here you can see is that the this characteristic and this character is completely symmetric after this point only what is happening the inversion is happening like n is saturation here and P is linear here so after this point p is saturation n is linear here B is linear n is cut off so here p is okay I wrote it opposite and your p is cut off and N is linear so the inversion is happening right after this point only so this point is known as switching threshold this exact point is known as switching threshold okay so when k n is 4 times okay P we are saying 4 times of k p and for this curve we have seen k n is k n is equals to KP and one more assumption we have made is that your v t n is equals to mod of vtp okay so we will take this vtn is equals to mod of vtp and and what when uh 10 is 4 times okay p and vtp is equals to vtn then what will be your v in v v in I will write it switching threshold so being switching threshold will be vdd plus 2 upon 3 right 4 2 yeah so 5 plus 2 by 3. 7 by 3. seven by three two two point six seven and that is greater than 2.5 volt right so so your switching threshold increased right so basically when we when not V when k n is greater than KP voltage transfer characteristics move away from origin right because at higher value of v in because at higher value of mean we will get the switching threshold right and when k n is KP by 4. what will happen and mode of vtp is equals to vtn so your v in switching threshold would be v d d Plus that is equals to 1 volt vdd plus 1 by 4 upon not one by four it would be one by two one plus one by two that means it would be 5.5 upon 1.5 foreign look over here we have done the mistake here this is 2.33 okay and this is less than 2.5 and we can't really generalize it like if k n is greater than KP it really depends on the formula okay we can't generate generalize it just assume KN is equals to just assume k n is equals to 2 KP k n is twice of KP and then try to find the value so it would be 5 plus root 2 upon 1 plus root 2 and that is greater than 2.5 okay so we can't really generalize the formula we can just write the formula for a specific case that we have seen okay Switching threshold decreased and when uh we can't really generalize it so what we will write when k n is equals to 4 KP okay and in this case it is equals to 3.66 that is equal greater than 2.5 then switching moves towards such towards here we will write towards move towards origin okay switching threshold increased okay so VTC moves away room origin okay so if there is a BTC drone like this V naught by V in okay I will just pause the video and do it so I didn't make that much wood but just to make you understand this is KN is KP by 4 right this is k n equals to KP and that would be k n equals to 4 KP right switching thresholder degrees that that means at lesser value of v in we will get into the saturation region here at the this value of v in we will get into the resolution and here at this value of p and we will get into the saturation okay so it is moving this time it is moving at this side okay so this is what is happening okay so this is the complete analysis I guess there is no single point is left so just revise whatever I have told okay so the main curve curve is this okay so you need to remember so for 0 to vtn P is linear n is cut off then one device can can't both divide situation of both device will not change only one will change from linear to linear it is going from cut off from saturation it is going from n is remaining same saturation to saturation now p is changing linear to saturation now then p is remaining the same any changing from suggestion to linear okay then p is p is changing and N is remaining the same so P concaturation to cut off and is linear to linear so that you need to remember concept you know okay the transformation you know K and KP value you know switching threshold VN value you know okay how does that change that you know okay so everything you know and why the Primo size is larger than animals that also you know so everything regarding CMOS University you know now we will just see One More Concept that is the current characteristics not character say I would say just that transfer statistic one one more transportation we will draw ID versus V naught okay so from there as well we will try to analyze something okay and you will see a very interesting concept there okay thank you hello everyone so now we will talk about the current okay so what we need to make is ID versus V naught okay that we are drawing ID versus V naught this is our task so four and moose V naught is equals to VDS and ID is equals to idn right so for nmos 4 nmos V node versus ID is basically VDS versus ID and that you already know linear saturation linear sublinear saturation increases the radius for saturation decreases okay and the value of value of ID decreases sorry if V increases value of ID increases and the saturation point also increases right so that you also know that you already know but in case of pmos there is something in case of pmos what is your V note V naught is we foreign OTE is ID is ID only so for nmos V naught uh we know these vdd minus vs okay so for nmos we need to do something so for Primos we can draw the transfer currency so 4 pmos for Primos we will draw it now not for pmo so for anniversary this is for nmos so this is ID versus v d s okay they will say VDS I don't need to explain it again right I have already explained it I have already explained everything oh no need to explain again again we will not draw for every every case so let us assume this is for v in equals to 1 volt so this will be for VN equals to 2.5 volt right and what will be for v in equals to zero volt this would be for being equals to zero volt and VDS is here equals to V naught only right so this is V naught versus ID curve basically now for nmos what do we already know so for nmos what do we already know is that [Music] here what did I write I write VDS now it should be VST so not this but we will draw like this only so this is vsd right this is VST versus ID okay we will try to explain it as much I as much as I can I will try to explain Okay so thank you so if this is the case right this is the case here okay so if array so this is the case this will be V in now this will be wind now tell me if we we the upper one would be larger or lower see this if vein is large your vsd is low if V in is large your vsd is low that means your current is low if V in is large your vhd is low that means your current is low so the upper one is the lower knob this is zero volt this is let us assume 2.5 volt and this would be V in equals to zero volt not zero volt five volt because when V in is equals to 5 volt PhD is zero that means zero current is there so that would be V equals to 5 volt now we have to draw I am writing and most look I have been decoding for so long right now that's why it is happening I guess we are talking about Primos here right ID versus PhD okay we are talking about pmos okay linear and then saturation but if V in is very high that means if V in is very high that means your vhd is very low that means your current is low if V in is low that means your current is high so that's why I have made the curve like this now I have to draw ID versus V node now your V naught is your V naught is vdd minus vsd can you draw the curve of ID versus V naught now ID versus V naught in the next page we will make ID versus V naught by D versus V naught okay so when when your V naught is equals to vdd that means your vsd is equals to zero V naught equals to vdd that means your vhd equals to 0 that means your current is 0. so when this V naught equals to v d that means your current is zero and your when your V naught is 0 when your V naught is 0 that means your vsd is equals to vdd right here vsd is equals to VD that means whenever the drain potential is low that means whenever the V node is low that means your current is high so the curve should shift something like this right this way it should go this way it should go and then there is this right or this way it should go it should go then this this will be for v in equals to zero right for being equals to V in equals to 0 and let us assume V in equals to what we have written 2.5 volt okay so if we have written 0 here we should write five volt here mean is 5 volt here and 2.5 volt here just and taking these value of 0 2.515 only okay so if 0 here 2.5 volt here and this one foreign equals to 5 volt right if v n equals to 5 volt if rain is equals to 5 volt then the current is zero okay okay the current is zero and whenever your VN is equals to zero volt the vsd is 5 volt that means the current is maximum and why this curve is from this side if you can replace it if you can replace the x axis then you can also things think like what is V naught V naught is vdd minus vsd so vhd just invert the vsd then shift it with vdt just take the mirror of this we need to make minus vsd Plus vdd so take the mirror of this and then shift it by vdd so we took the mirror of it then shifted it it by vdd so that so this is the curve that we are getting right so I will write it as well this is for pmos only for pmos what is happening is that your V naught is what is your what is your V naught that is minus VDS Plus vdd mirrored figure B this is figure a and this is figure B this is figure C so I mirrored figure B okay and added vdd Now by superimposing Now by superimposing by superimposing figure a and figure C so by C super important what do we add this is the final transfer characteristic that we get so this is the both of them look or this this these curves these curves these curves are for pmos and these curves are for nmos right these are for pmos look in this direction in this direction in this direction so what do we see here for v in equals to 0 this is the curve for V naught right now in case of nmos it is opposite for V inverse to five volt this is the curve foreign I naught versus V node curve okay I node versus V naught right now we can see something here look first thing we are seeing is that when V Nu is equals to 0 volt okay so in case of pmos in case of pmos what is the curve for VN equals to zero volt this is the curve right and in case of uh sorry in case of nmos in case of nmos whenever V is equals to zero this is the Curve this is in the case of nmos I should have written this is in the case of nmos so in case of nmos whenever VN is equals to 0 that means the current is zero so this is the curve right whenever V is equals to zero this is the curve and in case of pmos what is the curve for being equals to zero this is the curve of v n equals to 0. the VIN is same for pmos and nmos what I will write V in is same 4 both pmos and nmos in power CMOS inverter right in our CMOS inverter the VN is same for both pmos and nmos right initially VN is at zero volt if VN is at zero volt this is the case for nmos and this is the case for pmos so at what point the both of the curves are cutting at this point so at this point what is the value of V naught that is V2 take more examples take V in equals to one volt now v n equals to one volt so V in equals to 1 volt this is being equal to one volt right VN equals to one volt for Atmos this is v in equals to 1 volt for nmos right for Primos what is VN equals to one volt this is v in equals to one volt for pmos this is V equals to one volt for pmos so at what point they are cutting at what point they are cutting at this point at this point at this point at this point what do you see at this point what do we see the this is for pmos the pmos is in linear region and the nmos is in saturation region when we was one word just go to the curve when Vin was one volt the P pmos was in linear region and most was in saturation region here in the characteristics you can see that right here in the character see you can see that when this is the point of uh this is the point where both of the cuts are cutting right so this is the pmos curve the green one is Primos curve right the green one is Primos car so it is in saturation region and the this this what do we say whatever the color color it is so uh for that it is in linear region right okay did you understand now take V equals to 4 volt take V in equals to 4 volt this is V equals to four volt right this complete is being equals to 4 volt four nmos and for Primos what is v in equals to forward this is v in equals to forward and at what curve it is at this point at this point right so at v n equals to 4 volt this is the point right so at that point your p n MOS is in linear region and your pmos is in saturation region so is that the case just see here for 4 volts your for forward just before that your pmos region saturation region and your animals is in linear region right now for one volt we have talked about one volt we have talked about okay uh for now talking about 2.5 volt this curve for 2.5 volt and this is for 2.5 volt this is cutting right here right this is cutting right this is getting right here so what is V naught value V naught value is something here right that is VD by 2 and both are in saturation region and in this case for four volts this was getting here so what was the vdd value this so this was lesser than this this was lesser than VD by two so for v in greater than four or V in greater than four this was the value we were getting this was the value of V naught we were getting and here this was the value of V naught we were getting right so for V equals to 1 volt we are getting vdd to be high right or v n equals to 1 volt we are getting V naught to be I this is v d by 2. right this is divided by 2. so for v in equals to one word we are getting we know to be I so by simply this characteristics we can analyze the complete CMOS inverter okay if I if I had shown it earlier you wouldn't understand anything but now you have seen the complete analysis you have this curve as well just try to analyze this curve as much as you can okay this transfer characteristic is important okay in a very high class interview this will be asked okay so you can see that put V in equals to 1 your v v naught is higher than v d d by 2 also you can assume the region of operation as well that is that your pmos is in saturation region and your nmos is in linear region so this is the complete analysis so I guess you have understood it now you have to revise it completely and it will be all clear to you a CMOS inverter will be overflow we can see for few more question as well okay we will see that but it may seem complex to you but this is a easy topic if you understand it completely and I have given my best I guess whatever I have all the logic that I had all the concept that that I could deliver that I have delivered here and this current characteristics and all these stuffs this this is like this took me a lot of effort to understand by my by my own then to make it work on this writing part okay so I hope you have understood the concept and yeah so now we will move to some questions okay thank you hello everyone now we will try interchanging the pmos and nmos in the CMOS inverter okay so this is the CMOS inverter that we have seen right now we will change the position of animals and pmos and most will be going up and PMs will come down okay so first thing we need to see is that why do we need a CMOS inverter does for a high output it gives a lower for a high input it gives a low output and for a low input it gives a high output so for a High for a high input we want output to go all the way down to zero high input means if you have applied five volt here if it is five volt it is now from five volt we can't start actually if we have applied zero volt here let us assume for for a low input for a low input V1 output to go all the way up to 5 volt right if there is a low input that means if there is zero input here then this pmos will be 1 and this will be o if this pmos will be on then your V output steady state would be 5 volt right for a zero volt input your V output suggested would be five volt now when you have applied a high input if you applied a high input that means your VN is five then this will be off and this will be on then it will completely be recharged to zero volt the thing here is that your V naught steady state when V in is equals to 0 then your V naught steady state is what 5 volt it will be 5 or 4.3 taking VT to B1 taking V T to B one volt then it will be 5 Volt or 4 volt 4 volt why so because the pmos the condition for pmos to be one depends on these values right and for and most to be one depends on these values and this is dependent on the given Supply ground and the 5 volts and the given input okay so if your input is 5 this capacitor can completely be charged to fivefold because this is the drain terminal if it is at 4.3 then your vhd is greater than zero if it is at 4.4 then your vhd is greater than zero so till 5 volt it can charge right not 4.3 so it is going all the way up okay and when V in is equals to 5 volt what will be your Vino steady state when we need is equal to five four what will be we not statistic zero Volt or 0.7 volt zero volt because for 5 volt it will always be on if it is always on it will go go down to the value equals to Source voltage your VDS has to be greater than 0 for most to be on your VDS has to be greater than zero so here your VDS is always greater than 0 until the drainage is the zero voltage so this is the condition so here in this case your inverter in this CMOS inverter for a high input your output is going all the way down to zero and for a low input your output is going all the way up to five volt right now what happens is that we are interchanging it now when is equals to not five-fold first we will see Zero volt so that the capacitor charge so when V in is equals to zero volt [Music] will be on and your pmos will be oh now tell me what will be V naught steady state if it is 5 what will be venous research will it be 4.3 Volt or five volt 4.3 volt let us assume it goes to 4.4 volt if it goes to 4.4 volt this is five this is 4.4 VG no not 4.3 we have taken VT to V1 right VT to be one volt we have taken VT to be one volt so it will be four volt so let us assume it goes to 4.1 volt let us assume it goes to 4.1 volt so this is 5 volt this is 4.1 so this will be 0.9 and at 0.9 it will be oh so it can't really go above from four volt this Concepts we have already seen right in the capacitor problem in in the biasing problem we have seen most advising in that chapter we have already seen these problems so just reminding you that it can't go above four volt right because here the condition for mosfet to be on or off is depending on the Source voltage and that is your output voltage so your Source voltage is getting changed here so if your Source voltage goes above 4 volt it can't it can't be on so your window steady state is 4 volt and when is equals to zero volt your nmos will be oh right V naught degrees and your pmos will be oh this will be on now this is already charged to 4 volt what will happen it will get discharged so it will get discharged to work it will get discharged to zero Volt or one volt and VN is zero volt this is the zero volt so it will be discharged to one volt only let us assume it is it goes to 0.9 volt so vsg would be 0.9 V SG would be zero or nine that is less than mod of vtp that means that is less than one volt so your mouse will be oh right so it it's not getting it's not getting discharged to complete zero volt so the first thing you notice here is that for a higher for a high input 4 input or five volt you are getting a high output or a high input V in 4 equals to 5 volt you are getting a high output V naught equals to forward and the second is thing you notice is that you are not even getting the complete output like you want your output to go all the way up to you want your output to go all the way up to five volts but it is not happening okay so the thing first thing is that this is not acting like an inverter because for a high input you would want your output to be low but for a high input your output is high right it's acting like a buffer not inverter okay and the second thing is that your pull up output doesn't go all the way up to five volt and doesn't come down all the way to zero volt okay so they can ask you this question why can't we interject and when we interchange what would be the analysis that I also take us so these kind of questions can be asked so now you know the reason right the first thing is that it won't act as inverter the same thing is that your output is not going all the way up to five foot neither it is coming all the way down to zero volt okay I hope you have understood this concept okay thank you hello everyone so uh from from the first video onwards we are we are seeing the DC analysis of uh CMOS inverter first we applied the pulse input then we applied the ramp input then we interchange CMOS and animals all these things we do now we will see the small signal analysis small signal AC analysis you can say small signal AC analysis okay so now we have to see the small significance the first thing we will find is that what will be the voltage gain voltage again try writing the voltage gain by your own you can do it now okay so first let us draw the small signal model this will be shorted this will be shorted this will be shooted and this will also be sorted this is because this is the Supply right and this vs why I am shorting this this is vs this is PS and this is vs and here we have are not connected R naught one let us call it as M2 and M1 so this is R naught two and this is R naught one okay so this is the thing right now we have two vs voltage kind of we have two vs voltage although it is a one Supply only so kind of we have two vs voltage so we can apply superposition theorem right so applying superposition applying superposition what will be your v-note your V naught would be V naught by v s will be light again equals to V naught by v s would be look uh first we will consider this one to be short circuited and this one in action and most engine action okay if the animals is in action this is short circuited so here vsg is 0 right vsg is zero volt if this is zero volt then there will be no current this will be open circuited right if this is open circuited now from V node to ground we have R naught one and field from window to ground we have R naught two so R naught one and R naught two comes in parallel so this this side is open circuited and this R naught one is parallel to R naught two so the upper side is go now okay so now you need to see the Lower Side only so what will be the gain for it this is the common source amplifier and what is the gain minus GM minus g m 1 into R naught one parallel with r naught two right now in the next is what happens is that oh and you will write it again latest release of these things you wanted to write vsg0 vs is Source circuited BSG is 0 so avsd 0 that will be open circuit R naught one and R naught two will come in parallel so your gain would simply become minus gm1 are not one parallel with r naught two okay minus gm1 R naught one parallel with r naught two now talking about this one and this is shorted if this is shorted this would be one now because here vgs is 0 so this will be open circuited at zero current so this will be open circuited and this R naught one and r no two will come in parallel to each other right because V naught to ground we have R naught one and two so what will this become again this is the common source amplifier but this is the case of pmos right in case of pmos what will be the current flowing in this direction we will have GM vs current right because this is 0 this is vs so in case of uh pmos what is the current GM vsg what is the value of vsg now vsd is minus vs so GM vsd current is in this direction GM vsg what is the value of vsg now minus vs so GM into vs current is flowing in opposite direction so what will be the V naught value here in this direction if the current is Flowing so V naught would be minus GM into v s into resistance R naught one parallel with r naught two so what will what is the gain minus GM 2 into R naught one parallel with r naught two did you understand it just a simple analysis nothing else again in case of pmos as well it is becoming as a common source amplifier only okay if this is shorter this is gone R naught one comes in parallel with r No two this is source is common and we are collecting output and drain the source is common in case of pmos the source is common and we are collecting output at the drain terminal so what is happening there so this is simply a common source amplifier and what is the gain for common source amplifier in this direction so your V naught would be minus GM vs into R naught one parallel with r naught two so this will basically be minus GM 2 R naught one parallel with are not two okay so addition of both so basically what is your gain gain is minus gm1 Plus gm2 into R naught one parallel with node 2. okay did you get it minus minus sign is common g m one plus e m 2 into R naught one plus so this provides a gain of this this much okay so this is the voltage gain finding the output resistance foreign because these are the input source so this will be shorted so this will be gone this mod will completely be on this mod will completely be one so what what will remain are not one parallel is I'm not 2. right did you understand it vsbs is gone vsg is gone what is input resistance if input current is zero then what will be the input resistance it is Infinity because the input current this is the input current this is the input current these are zero only right so it would be infinity and what is the current gain okay current again I out by I in it would also be Infinity because the input current is 0 right the input current is 0. okay so this is the small signal analysis of CMOS inverter okay we will see a few more question now okay thank you hello everyone so this is the question uh we have to analyze the output voltage this is the configuration CMS inverter is given and the thing given is that t is very very greater than RC and this is the input that is given V equals to Vin is getting from 0 to 5 volt and then sinusoid input 5 Cyanogen basically Okay so try analyzing try analyzing it by your own just giving you a hint just try to break it in three reasons from zero to one volt from one to four volts and from four volts to again for all because this is sinusoid from zero to one one two four four two four four two all the way down to minus five and again that so you have to analyze it for 0 to T so how you will analyze it the first condition we can see is that when your v in is from 0 to 1 volt and V is 0 to 1 volt okay this animals will be off and pmos will be on now you don't need to if they are asking about these kind of imports you don't need to worry about the condition like pmos will be on but will it be linear or saturation that they don't wanna know they just want to know the steady state output the steady state output what will be V naught steady state if nmos is off and Primos is on what will be V not steady state this will be on and the let us assume this is five volt only okay so what will be we know steady state it will be five volt right this is 0 the the this is 0 to 1 let us assume this is 0.5 this is on vsg is 4.5 so this is on and this is O So if this is on this will this capacitor will charge all the way up to five volt so this is the steady set value we need to know so we will just draw the steady state value so for v in equals to 0 to 1 volt we have V naught equals to 5 volts right this is the 5 volt and secondly when Vin is greater than 1 and less than 4 volts okay so in this condition from 1 to 4 greater than 1 over equal to one so this will be one this will also be on pmo season and more 0 1. Primo season and more season now if V increases VN increases that means if V increases we can do one thing this we can call ID p and this we can call ID foreign and this we can call i d c okay so if V increases ID and increases and VN is increasing here vsg value is getting less VSC is getting less and here vgs is getting up here vgs is getting up so in case of nmos the current increases but in case of pmos your vsg is getting less if vsg is getting less that means your current is decreasing and your ID p is decreasing so these two things are happening if VN is increasing idn is increasing IDP is decreasing okay if IDP is decreasing that means let us assume this is 1 ampere this is 4 ampere so there has to be three three ampere current from this side right this is one ampere this is 4 ampere so there has to be 3 ampere current from this side right so that's why we have made the direction of IDC like this so that means your IDC increases right that means capacitors starts discharging so initially it was just to five volt now till what value it can discharge it was charged to five volt right this was just to 5 volt so till what value it can discharge zero volt because this is the CMOS inverter and this is the correct correct system and you can also see this is the drain terminal okay so the the condition for mosfet to be on and off doesn't depend on the drain terminal right the condition of four and most of pmos to be on or off it doesn't depend on that drain terminal until your vsd or VDS is greater than zero so if it goes to zero volt your vsd would be greater than 0 and your VDS would also be greater than 0 until it goes to zero volt right so from 5 volt to it completely recharges to zero volt so that's how we start scroll down and completely discharges to zero volt okay fine so this is for one two four volt okay so V naught steady state would become 0 1 this is the second one and now here we will see V in greater than 4 volt and less than 5 volt okay from 4 to 5. what will happen if it is 4.1 this will be of your pmos would be off and your nmos would be on okay now if if this is on but what is the value of V naught V naught is already zero volt so what will happen it will remain at 0 volt only right this is off and this is on there is no Supply here in case of animals there is no Supply this zero volt will remain at zero volt only this is the conditioner this is the condition upper one is off so if this is at zero volt this will remain at zero volt only right so this will remain at 0 volt so V naught remains at zero volt okay so this is the condition and four fourth one is if V in is negative if V in is negative from four to five volt that means we have analyzed for this this this strand right we have analyze first things complete for half cycle if VN is negative then your um this will be on yeah if your yeah if your VN is negative then your pmos will be on pmos on and most is o that means your V node study set would be 5 volts right if this is on and this is all so we know steady state would be 5 volt okay just we are analyzing it for these kind of VN is negative so it will be we know statistic would be five volt okay so let's see it here so for this cycle we have seen after that your VN is greater than V or V in is between four to five volt when your VN is between four to five volt what is your V naught remains at zero volt only so your V naught will remain at zero volt only okay so V naughty is remaining at zero volt now your V is between one to four volt if your V is between one to four volt what happens is that the capacitor starts discharging uh now we are getting no no from four to one we are going right we from four to one we are going from 4 volt to one volt so for let us assume at 3.9 what will happen 3.9 this will also be on and this will also be on right but the value of VN is getting decreased now look V in is we are going from 4 to 4 volt to 1 volt right we are going from 4 volt to 1 volt so add V in equals to 3.9 volt both are on right pmos is on and nmos is also on okay if V in is decreasing VN is decreasing a v n is decreasing then this current in current in nmos is decreasing and the current in pmos is increasing because if green is decreasing then your BSG is increasing so current in N pmos is increasing and in your nmos is decreasing so let us assume this is 4 ampere this is one ampere so 3 ampere has to go down in this direction right right so capacitor charges if your vein is degreasing that means your idn is decreasing and your IDP is increasing that means your capacitor charges so it's charges and charges charges up to charge it up to four volt 5 volt right so from we are coming this is the fifth condition from four to one volt the capacitor charges and it will charge up to 5 volt so it will charge up to 5 volt one more thing we can do here is that now if we are coming down from one to zero volt ah this is the condition VN is coming down to one volt to zero volt so let us Zoom zero volt so let us assume at 0.9 at 0.9 volt what will happen this pmos is on and this is this is off okay so if this is on then your V naught steady set would be 5 volt only when Vin is 0.9 so this will animals is off and your pmos is on so here your nmos is oh and your pmos is on that means a v naught steady state is 5 volt only right and for the negative cycle what happens for the negative cycle we know statistic is five volt only now it will always remain at 5 volt till time t this is the time t so till time T it will remain at 5 volt only right and you understand it let us call this time even T2 these are the time span so I hope you can see the curve now okay so this is not that uh complex problem but just we need to see from 0 to 1 volt we are going pmos is on and more zero so it will remain at 5 foot from one to four volt we are coming from one to four volt we are going so both of the transistor are on Primo season and more season but you need to see the current if we increases your ID is increasing that means your capacitor is getting discharged so it will discharge from five to zero volt only okay now the third condition is that when we when we are going for 4 volt to 5 volt if we are going from four to five your pmos is on and most is pmos is off and animos is on if animal is on there is no Supply so it will remain at zero volt only now we are from five to uh from four to five then we are coming from four to five and then from five to four right we are coming down from five to four then it will remain same only because the Primos is off and nmos is on now we are coming down from 4 volt to 1 volt okay from four volt to one volt we are coming down so at let us Zoom at v n equals to 3.9 what happens pmos is on and no season so if V is decreasing then your ID is decreasing IDP is increasing then your capacitor is charging then it charges from 0 to 5 volt then after one volt what is happening from one to zero volt both of the uh and most is off and Primos is on that means your capacitor charges so steady set value is five volt so it will remain at five volt and in negative cycle we have already seen your V naught remains at five volt only so this is how it goes okay and this thing that I have written here should not come here it should come in last right look at that we will write down here only what we will write down this will be the sixth point if V in is negative that means your pmos is phone and your nmos is oh then V naught steady state would be five volt only Okay so this will be fifth and this will be fourth this should be erased okay so this is the complete analysis I hope you have understood it this was a very good issue okay thank you