TI Precision Labs: PCIe Lecture

Jul 20, 2024

TI Precision Labs: PCIe Lecture

Introduction to PCIe

  • Full name: Peripheral Component Internet Connect Express
  • Introduced: 2003
  • Primary motherboard expansion bus standard
  • High-speed serial communication between CPU and peripherals
  • Replaced older parallel buses

History and Development

  • Predecessor: PCI (90s)
  • PC Bus standards: Designed for CPU-device communication via expansion slots
  • 2003: Introduction of PCIe serial bus to replace parallel buses
  • Iterative improvements: PCIe 6.0 in 2021, enabling 64 Giga Transfers/second
  • Unique feature: Ability to increase number of lanes from 1 to 32

PCIe Communication

  • Hierarchical Structure
    • Single source of data: Root Complex
    • Information passes from multiple PCIe endpoints
  • Typical Link Components
    • Root Complex: Interface between CPU/memory and PCIe structure (integrated into CPU or a discrete component)
    • Repeater: Signal conditioning device (Retimers and Redrivers)
    • Endpoint: PCIe end component (e.g., GPU)

PCIe Control Signals

  • PERST: Fundamental reset, transitions from low to high indicate link initialization
  • WAKE and CLKREQ: For transitioning to/from low power states (refer to separate video on link training)
  • REFCLK: 100 MHz reference clock required to begin data transmission

Link Initialization and Data Transfer

  • Post-Power Up: Devices detect link partners
  • Transmission begins at 2.5 Gbps (PCIe 1.0/Gen 1 speed)
  • Polling State: Devices transmit ordered training sequences to establish bit/symbol lock
  • Configuration State: Lane to lane alignment and determining link width and lane numbers
    • Single non-bifurcated connection example
    • Retimer splits link into two parts, initialized separately
  • L0 State: Normal operational state where data packets are sent and received
    • Possible states: Low power, link training (recovery), L0 (for data transfers)

Link Speed Optimization

  • Devices supporting PCIe Gen2 or higher can increase data rates
  • Gen 3 and Higher Speeds: Requires link equalization
  • Link Equalization (Link Eq): Modifies transmitter data waveform characteristics
    • Uses preset configurations (0-10) for Gen 3 and 4
    • Phases of Link Eq:
      1. Phase 0: Downstream sends desired transmitter presets to upstream
      2. Phase 1: Link data rate increases to Gen 3; upstream sends training sequences
      3. Phase 2: Further optimizes upstream port preset values
      4. Phase 3: Further optimizes downstream port preset values
  • Conclusion of Link Eq: Achieves a bit error rate of less than 10^-12
    • Signal conditioning (e.g., retimer) may be required for long channel links

Additional Resources

  • PCIe and PCI support: e2e.ti.com (Interface section)
  • More on signal conditioning: TIPL series presentations