Hey, friends welcome to the YouTube channel ALL ABOUT ELECTRONICS. So in this video, we will see that, how to design the logic gates using the CMOS logic. So if you see any logic gates, then it's characteristic like fan-out, voltage level, speed, and power consumption, depends on the technology, which is used to design this logic gates. Now there are different logic families, but some of them are already obsolete. But some of the logic families, like the TTL, CMOS and the ECL are quite popular, and they are widely used in the digital circuits. So in this particular video, you will learn about the CMOS logic family. So this CMOS stands for the complementary metal oxide semiconductor. And the CMOS based logic gates, uses the complementary pair of the NMOS and the PMOS transistors. So when the MOS transistors are used as a logic gate, then they are used as a switch. So in both, NMOS and the PMOS transistor, the voltage which is applied between the gate and the source terminal will act as a control voltage. So in the NMOS transistor, when the gate to source voltage is less than the threshold voltage, then the NMOS transistor will act as an open circuit. And when this voltage is more than the threshold voltage, then this NMOS transistor will act as a close switch. Similarly in case of the PMOS transistor, this threshold voltage is negative. So when this voltage between the source and the gate terminal is less than the threshold voltage, then the PMOS transistor will act as a open circuit. And when this voltage is more than the threshold voltage, then it will act as a closed switch. So in this way by controlling the gate to source voltage, this PMOS and the NMOS transistor can be used as a switch. And in this way, they can be used to design the logic gates. So this CMOS logic gates uses the complementary pair of the NMOS and the PMOS transistor. The PMOS transistors are used as a pull-up network, while the NMOS transistors are used as a pull-down network. And because of that, the static power consumption of the CMOS based logic gates, and the logic circuits is very low compared to the logic gates which is designed using only either NMOS or the PMOS transistors. Not only that, the CMOS based logic gates has higher noise margin compared to the logic gates, which is designed only using the NMOS or the PMOS transistors. And that is the biggest advantage of the CMOS based logic gates. So step by step we will understand that in the CMOS based logic gates, why the NMOS is used as the pull down network, and why the PMOS transistors are used as the pull up network. And why the CMOS best logic gates consumed very low power. And after that we will see that, how to implement the different logic gates using the CMOS logic. So just using either NMOS or the PMOS transistor also, it is possible to design the logic gates. For example, this is the basic design of the NMOS inverter. So when the voltage between the gate to source terminal is more than the threshold voltage, let's say a 5 Volt or the logic 1, then this mosfet will act as a closed switch. And in this way the output will get connected to the ground terminal. Now ideally in this condition, the resistance of the mosfet should be equal to 0. But actually there will be some ON resistance of this mosfet. Typically it is in the few ohms. While if you see the drain resistor, then its resistance is in kilo ohm. That means here when the input is equal to 5 Volt or the logic 1, then the output is very close to the logic 0. Likewise when the input is equal to 0 volt, then the gate to source voltage is less than the threshold voltage. Let's assume that, here the threshold voltage of the mosfet is equal to 0.5 volt. So when the Vgs is less than the threshold voltage, then the mosfet will act as a open switch. And therefore through the drain resistor, the output will get connected to the supply voltage. That means whenever this input is equal to 0, then the output is very close to the Vdd. Or in this case, it is equal to 5 volt. And in this way this circuit will work as the inverter. Now when we are designing the logic gates using the discrete components, then it is possible to include the last drain resistor in the circuit. But in the integrated circuits, it is difficult to fabricate a resistor with the large value. So in the integrated circuits instead of a resistor, the mosfet is used as the active load. So as you can see over here, for this mosfet the gate and the drain terminals are connected to the Vdd. That means this upper NMOS transistor will remain in the ON condition. And in the ON condition its ON resistance will provide the required drain resistance, for the lower NMOS transistor. So of course by changing the mosfet device parameters, like a W/L ratio, it is possible to ensure that, its ON resistance is in kilo ohm. And in this way, this mosfet can be used as the active load. Now in this circuit, when this input is equal to low, then this lower NMOS transistor will remain off. And in this case the output of the inverter will be equal to high. And similarly where the input is high, then this lower NMOS transistor will act as a close switch. And in that case the output of this inverter will be equal to low. And in this way it is possible to implement the NMOS inverter using the active load. Now the issue with this design is that, there is a static power dissipation across this NMOS transistors. For example when the input of the inverter is equal to high, then the NMOS transistor will act as a closed switch. And it will provide the very low resistance. And in this condition, there will be a flow of current, from the drain to the ground terminal. And because of that, there will be a power dissipation across this NMOS transistors. For example if the input to the inverter is equal to clock signal, which is continuously changing between the logic 1 and the logic 0, then for the half of the total time period of the clock signal, there will be a static power dissipation across this NMOS transistors. And the same is the case with the logic gates which is designed using the PMOS transistors. That means whenever we are designing a logic gates using either NMOS or the PMOS transistors only, then there will be a static power dissipation across this transistors. And this power dissipation becomes a critical factor, whenever there are millions of such transistors in the circuit. So apart from this power dissipation, the other issue with the design is that, this NMOS passes weak logic 1. That means, whenever the input to the logic gate is equal to logic 0, then ideally the output should be equal to Vdd. Or in this case it should be equal to 5 volt. But actually here the output voltage will not go beyond the Vdd minus VT. So let's say here the threshold voltage of the mosfet is equal to 0.5 volt. That means in this case the output voltage will not go beyond the 4.5 volt. Because here, if the output of the inverter goes to the Vdd, or in this case if it goes to the 5 volt, then the source terminal of this upper NMOS transistor, will be at the 5 volt. And in this case if you see, then this Vgs is equal to 5 minus 5 volt. That is equal to 0 volt. So in this condition if you see, then this VGS is less than threshold voltage. And in this condition, the mosfet will not remain in the ON condition. That means the voltage at the source terminal will not go beyond the Vdd minus VT. Or in this case, it will not go beyond the 4.5 volt. That means here we will not get the full voltage swing. Or in other words this NMOS transistor is weak to pass the logic 1. On the other end, this NMOS will pass strong logic 0. So for example if the input to the inverter is equal to logic 1, then this lower NMOS transistor will be in the ON condition, hence since the source is connected to the ground terminal, so it will also pull down the voltage of this drain terminal to the zero volt. And because of that, the output of the inverter will be equal to 0 volt. So as you can see this NMOS passes a strong logic 0, but it passes weak logic 1. That means as you can see this NMOS transistor is not a good choice for the pull up network. But it can be used in the pull-down network to pull down a voltage of the specific node to the 0 volt. On the other end if you see the PMOS transistor, then it passes strong logic 1. For example, here the source of the PMOS transistor is connected to the 5 volt. And the drain terminal is connected to the capacitor. Now when this input to the PMOS is equal to logic 0, or whenever this gate terminal is connected to the ground terminal, then here this VSG is more than the threshold voltage. And because of that this PMOS will act as a close switch. So now the capacitor at the drained terminal will start charging towards the 5 volt. And eventually the voltage across the capacitor will be equal to 5 volt. That means whenever we want to pull up the voltage at the drain terminal to the supply voltage, then we can use this PMOS transistor. That means this PMOS transistor passes strong logic 1, but at the same time it is weak to pass logic 0. So for example let's say now the drain terminal is connected to the ground terminal, while the capacitor is connected at the source terminal. And let's assume that the initial voltage across the capacitor is equal to 3 volt. So now whenever this VG is equal to 0, then this VSG is more than the threshold voltage. And because of that this PMOS will conduct, and it will try to bring down the voltage of the source terminal to the 0 volt. That means now the capacitor will start discharging. But as soon as the voltage at the source terminal reaches the threshold voltage of the mosfet, then the mosfet will get turned off. Because now this Vgs is equal to VT. And in this condition the capacitor will stop discharging. That means in this condition, the voltage at the source terminal cannot go below the threshold voltage. So for example, if the threshold voltage of this PMOS transistor is equal to 0.5 volt, then the voltage at the source terminal will not go below the 0.5 volt. That means this PMOS transistor passes weak logic 0. That means whenever, we want to pull down the voltage of the specific node to the logic 0, then it is not preferable to use the PMOS transistor. That means this PMOS transistor is not preferable to use in the pull down network. But it can be used in the pull up network, where we want to pull up the voltage to the specific node. So in the CMOS logic gate both PMOS and the NMOS transistors are used. So this PMOS transistor is used as a pull-up network, while this NMOS transistor is used as a pull-down network. And because of this configuration, we will get the full voltage swing for the logic 1, as well as the logic 0. Or in other words, we will get the higher noise margin. Not only that because of this configuration, there is almost no static power consumption in the PMOS logic gates. So this is the circuit of the CMOS inverter. So as you can see over here, this PMOS is used as a pull up transistor, that means here its source terminal is connected to the supply voltage, while the drain terminal is connected to the output node. Similarly this NMOS transistor is used in the pull-down network. That means here, the drain terminal of this NMOS transistor is connected to the output node, while the source terminal is connected to the ground terminal. And as you can see the gate terminals of the both transistors is connected to the input node. So when the input is equal to logic 0, then for this PMOS transistor this VSG is more than the threshold voltage. And that is why this PMOS transistor will remain in the ON condition. On the other end for the NMOS transistor, this Vgs will be less than the threshold voltage. That means in this condition, this NMOS will remain off. That means whenever, the input to the CMOS inverter is equal to logic 0, then the PMOS will be in the ON condition, while the NMOS will be in the off condition. And because of that, this output will get connected to the supply voltage. Moreover since the PMOS passes a strong logic 1, so the output will be very close to the supply voltage. That means whenever this Vin is equal to logic 0, then the output is equal to logic 1. On the other end when this Vin is equal to logic 1, or in this case, when this Vin is equal to 5 volt, then the PMOS will remain off, while the NMOS will remain ON. Because for this PMOS transistor, if you see the value of the VSG, then that is equal to 0. And since it is less than the threshold voltage, so this PMOS transistor will remain in the off condition. On the other end, for the NMOS transistor, if you see, then this Vgs is more than the threshold voltage. And due to that, this NMOS transistor will remain in the ON condition. So in this case this NMOS transistor will pull down the output voltage to the logic 0. And since NMOS passes a strong logic 0, so this output voltage will be very close to the 0 volt. So in this way, this circuit will work as the inverter. And if you see over here, then at any given time either PMOS is ON, or the NMOS is ON. But both transistors are not on at the same time. And in this way, there is a no direct path from the supply voltage to the ground terminal. And because of that the static power consumption of the CMOS logic gate is almost negligible. But the CMOS logic gates do have a dynamic power dissipation. But we will talk about it at the later part of the video. But in short the CMOS based logic gates have a very low power consumption, and they also provide high noise margin. So in general if you see any CMOS based logic gates, then it consists of a pull-up network, and the pull-down network. The pull-up network consists of the PMOS transistors, while the pull-down network consists of the NMOS transistors. And the inputs to the both networks are same. So we have already discussed about the CMOS inverter. Similarly let us see how to design the other logic gates using the CMOS logic. Now in many textbooks and many literatures the alternate symbols of the PMOS and NMOS transistors are used. So this is the alternate symbol for the NMOS transistor, while this is the alternate symbol for the PMOS transistor. So from now onwards we will use this alternate symbols during our discussion. So this is the circuit of the CMOS inverter using the alternate symbols. Similarly we can also design a two input NAND gate using the CMOS logic. So first let us see how to implement the NMOS network. So here for the two input NAND gate this output Y is equal to this A dot B whole bar. So in the NMOS network, when we have an end operation between the two variables, then the two NMOS transistors will get connected in the series. And the output of this NMOS network will be the complement of this A dot B. So this is the implementation of the NMOS network. And similarly if you see the PMOS network, then it is the dual of the NMOS network. So in the NMOS network if the two transistors are connected in the series connection, and in the PMOS network the two PMOS transistors will get connected in the parallel connection. So this is the overall circuit of the two input NAND gate. So now let us see the working of this circuit, and let us understand how this circuit indeed work as a NAND gate. So this is the truth table of the two input NAND gate. So whenever both A and B are 0, then both PMOS transistors will be in the ON condition. While if you see the NMOS transistors, then both transistors will be in the off condition. And because of that this output will get connected to the Vdd. That means whenever both A and B are 0, then the output of the NAND gate is equal to logic 1. Similarly when this A is 0 and B is 1, then the first PMOS will be ON, while the second PMOS will be off. And since both the PMOS are connected in the parallel connection, so if any one of the PMOS is ON, then also the output will get connected to the Vdd. On the other end if you see this NMOS network, then the first transistor will be off, while the second transistor will be ON. So for the NMOS network since both NMOS are connected in the series connection, so the output will get connected to the ground terminal only when, when both and most transistors are ON. That means here, for the second case, this NMOS network will remain open. And that is why, here this Vout is equal to VDD. And the same is the case for the third input combination. And lastly, when both A and B are 1, then both the most transistors will remain in the off condition. On the other end if we see the NMOS transistors, then both NMOS transistor will remain in the ON condition. And in this case, since both NMOS are ON, so the output will get connected to the ground. That means in this case this output to the NAND gate is equal to logic 0. So in this way this CMOS base implementation will work as a two input NAND gate. So similarly we can also implement the three input NAND gate. So here if A B and C are the inputs to the NAND gate, then its output will be equal to A dot B dot C whole bar. So for a moment let's forget this bar, and let us implement this NMOS network. So here since we have a end operation between this A B and C, so all the three NMOS transistors will get connected in the series connection. And if you see the PMOS counterpart, then three PMOS transistors will get connected in the parallel connection. So in this way, we can also implement the three input NAND gate using the CMOS logic. So similarly now let us implement the two input NOR gate. So for the NOR gate if A and B are the inputs, then its output will be equal to A plus B whole bar. So once again first let us implement the NMOS network. So we know that, by default the output of the NMOS network will get inverted. So for a moment, if we just ignore this bar, then here we have a A plus B. So here since we have OR operation between the two variables, so in the NMOS network the two NMOS transistors will get connected in the parallel connection. And if you see the PMOS network, then it will be the dual of the NMOS network. So here in the NMOS network since both transistors are connected in the parallel connection, so in the PMOS network both will get connected in the series connection. And in this way, this is the CMOS implementation of the two input NOR gate. Similarly we can also implement the two input OR gate. So we have already seen that, how to implement the NOR gate. So if you want to implement the OR gate, then we just need to connect the inverter at the output. And the output of this inverter will be the output of the OR gate. Similarly to implement the two input AND gate, we just need to connect the inverter at the output of the NAND gate. So in the CMOS implementation inherently, we are getting the inverted output. So here it is easy to implement the NAND and NOR gates compared to the AND and OR gates. Moreover the implementation of the NOR and the NAND gates will require less number of transistors compared to the OR and the AND gates. All right, so, so far we have seen that, how to implement the five different logic gates using the CMOS logic. So similarly now let us see how to implement the two input XOR gate, and the XNOR gates using the CMOS logic. And first let us see the implementation of the XOR gate. So if we see the expression of the two input XOR gate, then it is equal to this A bar B, plus A dot B bar. Or in other words, it can be written as this A B plus this A bar B bar whole bar. That means the output of the XOR gate is the complement of the XNOR function. So first let us implement this NMOS network. So for a moment if we just remove this bar, then we will have this A dot B, plus A bar dot B bar. That means here both A and B will be in the series connection, while the A bar and B bar will also be in the series connection. And then the combination of this A B and the A bar B bar will get connected in the parallel connection. So this is the implementation of the NMOS network. Similarly if we see the implementation of the PMOS network, then it is the dual of the NMOS network, that means in the PMOS network, this A and B will get connected in the parallel connection. And similarly this A bar and B bar will also get connected in the parallel connection. And after that, in the parallel combination of this A B and the A bar B bar will get connected in the series connection. So this is the CMOS implementation of the XOR gate. So in case if you want to verify the logic of this implementation, then you can verify that by using the truth table of the XOR gate. So for each input combination, you can verify that you are getting the correct logical output. For example when both A and B are 0, then in this PMOS network, these two transistors will be in the ON condition. On the other end, this A bar and B bar will remain in the OFF condition. Similarly if you see the NMOS network, then for the NMOS network, this A and B will remain off, while this A bar and B bar will remain in the ON condition. And through these two transistors, this output will get connected to the ground terminal. That means in the first case, this output will remain low. And in the same manner you can also verify the output for the other input combinations. So this is the CMOS implementation of the XOR gate. So lastly now let us see the CMOS implementation of the XNOR gate. So for the XNOR gate, if A and B are the inputs, then its output Y is equal to A dot B plus A bar dot B bar. Or in other words, it is the complement of the XOR gate. So we can write it as this A bar B, plus A dot B bar whole bar. So for the given expression, this is the NMOS implementation. So as you can see over here, this A bar and B are in the series connection. And similarly this A and B bar are also connected in the series connection. And since we have A plus sign between this A bar B and the A dot B bar, so this two input combinations will get connected in the parallel connection. So basically this is the NMOS implementation for the given expression. Similarly if we see the PMOS implementation, then it is the dual of the NMOS network. That means in the PMOS network, this A bar and B will get connected in the parallel connection. And similarly this A and B bar inputs, will also get connected in the parallel connection. And after that these two parallel combinations will get connected in the series. So this is the CMOS implementation of the XNOR gate. And here during our implementation, we have assumed that the complement of the A and B are already available. But if they are not available, then we can derive that with the help of the inverters. So in this way in a similar fashion, we can also Implement any Boolean function with the help of the CMOS logic. All right! So like I said earlier, there is almost no steady power consumption in the CMOS logic gates. But actually, due to some leakage current through the transistors, there will be some static power consumption. But apart from the static power consumption, there will also be a dynamic power consumption in the logic gates. And compared to the static power consumption this dynamic power consumption will be very high. And therefore for time being, we can assume that, the static power consumption of the CMOS logic gate is almost negligible. So, so far during our implementation, we have assumed that, the nothing is connected at the output of the logic gate. But actually the output of the logic gate will get connected to some other logic gate. So because of that, there will be a load capacitance at the output of the logic gate. That means when we connect the output of the logic gate to the next stage, then the inputs of the next stage will have some input capacitance. Typically the gate capacitance of the inputs will act as a load capacitance for the previous stage. Moreover the interconnects between the two logic gates will also add some capacitance. So because of this load capacitance, the output of the logic gate will take certain time to charge from logic 0 to logic 1, or to discharge from logic 1 to logic 0. And during the charging and the discharging of this capacitor, there will be some dynamic power consumption across the logic gate. So in short whenever there is a transition in the output of a logic gate, from 0 to 1, or 1 to 0, then this load capacitor will get charged or discharged. And during that time there will be a power consumption in the logic gates. Moreover because of the finite rise time in the fall time of the inputs, there will be a finite time during which, both NMOS, and the PMOS transistors will be in the ON condition. And during that finite time, the current will flow between the supply and the ground terminal. So because of that, there will be a power dissipation across the CMOS logic gate. So these are the two factors which will contribute in the dynamic power consumption. But still if you see the overall power consumption of the CMOS circuits, then it is much lesser than the other logic families. And that is the biggest advantage of the CMOS based circuits. So that's it for this video. And I hope in this video you understood, how to implement the logic gates using the CMOS logic. And you also understood what is the advantage of the CMOS logic gates. So if you have any question or suggestion, then do let me know here in the comment section below. If you like this video, hit the like button, and subscribe the channel for more such videos. [Music]