Lecture Notes: Digital Design and Computer Architecture

Introduction

• Welcome to the lecture on digital design and computer architecture.
• Focus on timing and verification.
• Recommended readings for this week and next.

Circuit Timing

• Logical vs. Real-world Implementation

  • A logically correct design can fail due to implementation issues.
  • Digital logic assumes immediate output changes, but in reality, outputs are delayed due to transistor switching times.

• Combinational Circuit Timing

  • Not Gate Timing: Output changes aren't immediate; delays occur.
  • Buffer Gate Timing: Delays due to capacitance and resistance.
  • Latency Types:
    • Contamination Delay: Delay until output starts changing.
    • Propagation Delay: Delay until output stops changing.

Delay Causes and Effects

• Delay is caused by capacitance and resistance.
• Different input vectors and environmental changes (temp, voltage) affect delays.
• Aging of circuits increases latency.
• Design Considerations:
  • Calculate longest and shortest delay paths.
  • Critical path defines maximum delay.

Dealing with Delays

• Propagation Delay Examples:
  • NAND gate delay varies with voltage and temperature.
  • Different implementations (e.g., multiplexers) have different delays.
• Glitches:
  • Caused by different path delays.
  • Fixing glitches may consume more area and power.

Sequential Circuit Timing

• D Flip-Flop (DFF):

  • Data must be stable at the clock's active edge.
  • Setup Time: Time before clock edge data must be stable.
  • Hold Time: Time after clock edge data must be stable.

• Sequential Systems

  • Proper setup and hold times ensure correct operation.
  • Clock Cycle Time Constraints:
    • Must be longer than the sum of propagation delays and setup time.
    • Holds time constraints affect how soon data can change after a clock edge.

Clock Skew

• Clock Skew: Time difference between clock signal arrivals at different parts of the chip.
  • Affects setup and hold time constraints.
  • Designers minimize skew to maximize performance.

Circuit Verification

• Functional Verification:

  • Ensures logical correctness.
  • Simulation: Using HDL and C simulations.

• Testbenches:

  • Used for testing devices under test (DUTs).
  • Types: Simple, Self-checking, Automatic
  • Golden Model: Used for more accurate verification.

Timing Verification

• Approaches:

  • High-level simulations with delays.
  • Circuit-level simulations using tools like spice.
  • Tools provide timing reports.

• Fixing Timing Errors:

  • Adjust synthesis and placement.
  • Manually optimize design.

Conclusion

• Verification is crucial and complex.
• Timing and verification encompass a substantial portion of design work.
• Next week: Transition to computer architecture.