Understanding Latches and Flip-Flops

Hey friends, welcome to the YouTube channel ALL ABOUT ELECTRONICS. So in this video, we will learn about the basic memory elements which are used in the sequential circuits. So in the previous video, we have seen that this memory element is very essential and the basic building block of any sequential circuits. So basically, there are two types of memory elements. which are used in the sequential circuits. That is latch and the flip-flop. Well, both the memory elements are able to store one bit of information. That means their output can be either 0 or 1. And since they have the two stable states, so they are also known as the bistable multivibrator. So in this video, let us understand what is latch and flip-flop and what is the basic difference between two of them. So first of all, Let's start with the latch. So this latch responds to the input level change immediately. For example, let's say initially the input of this latch is equal to 1. And based on that, the stored value in the latch is equal to 1. Now suddenly, if the input level changes to 0, then the latch will also immediately respond to that input level change. And based on that change, it will also change the output stage. So basically it is the asynchronous type of memory element. So this type of latch which immediately responds to the change in the input are called transparent latch. Now there is another type of latch which becomes transparent based on the control input. So this latches are known as the gated latch. So as you can see this gated latch also has enable input. So when this enable input is high then this latch is transparent to the input. That means when this enable input is high, then the latch responds to the change in the input immediately. And when this enable input is low, then even if the input changes, then it does not respond to that input change. And in that case, it retains its previous state. Now when we apply the periodic clock signal to this enable input, then the same gated latch can be used as the synchronous memory element. Because now This latch will respond to the input when the clock signal is high. And it will remain in its previous state when this clock signal is low. So as you can see, basically it is sensitive to the clock signal level. But during this on time of the clock, if the input level changes, then it will respond to that change immediately. So let us understand the working of this gated latch with the help of the timing diagram. So let's see. Here we have one gated latch and the clock signal is applied as the enable input. So here the signal which is shown in the blue color is our clock signal. And that signal is applied at the enable input. So as you know this gated latch will become transparent when the clock signal is high. Or in other words when this enable input is high. So as you can see during the on time of this clock signal when the enable input is high, then the output of the latch is same as the input signal. And after that, when this enable input becomes low, then even if the input signal changes, then also this latch will not respond to that input change. And as you can see, it is retaining its previous state. So in this case, during the off time, it will remain 0. Now once again, during the on time of the clock, when the enable input becomes high, then once again, the output will follow the input signal. So as you can see, during this time, this output is following the input signal. And once again, during the OFF time of the clock signal, it will retain its previous state. So as you can see, during this OFF time, the input is going from HIGH to LOW. But still, this latch will not respond to that input change. And it will retain its previous state. Now once again, it will become transparent to the input. when the clock signal is high. Or in other words, once again when the enable input is high. So at that time, since the input is low, so the output will also become low. So this is the output of this gated latch. And as you can see, when this periodic clock pulse is applied at the enable input, then this gated latch will become level sensitive memory element. That means it will become transparent when this clock signal is high. On the other end, If you see the flip-flop, then it also has clock input. And it responds to the input only at the clock transition. That means the flip-flop is the edge-triggered memory element. On the other end, if you see the latch, then it is the level-triggered memory element. Now this flip-flop can respond to the input either at the rising edge or the falling edge of the clock signal. So if it responds to the input at the rising edge, then it is called as the positive edge-triggered flip-flop. On the other end, if it responds to the input at the falling edge of the clock, then it is called as the negative edge-triggered flip-flop. So, through the timing diagram, let us understand how this edge triggered flip-flop behaves to the input level changes. And first, let us take the case of the positive edge triggered flip-flop. So here, the same signal which we have applied to the gated latch is also applied to the flip-flop. And this signal which is shown in the blue color is our clock signal. So since the flip-flop is the edge triggered flip-flop, so it will respond to the input at the rising edge of the clock. And here we are assuming that at the clock transition, the flip-flop follows the input signal. That means at the clock transition, if the input is high, then the output of the flip-flop is also high. And if the input is low, then the output of the flip-flop will also become low. So based on that assumption, let us see what will be the output of this flip-flop. So as you can see, at the first rising edge, the input is high. That means the output will also become high. But now, the flip-flop will respond to the input at the next rising gauge. And till that, it will retain its previous stage. That means in this case, until the next rising gauge, it will remain high. That means up to this point, the output of the flip-flop will remain high. Now once again, at the next rising gauge, the input is once again high. That means during the next clock transition also. the output will remain high. And it will remain high until the next clock transition. So in between, even if the input level changes, then also it will not respond to that input level change. So now at the next clock transition, since the input becomes low, so the output will also become low. And it will remain low till the next clock transition. So as you can see, this is the output of this positive edge triggered flip-flop. Similarly, for the same inputs, let's see the output of this negative edge triggered flip-flop. So this negative edge triggered flip-flop will respond to the input at the falling gauge. So till the first falling gauge, the output of the flip-flop will remain 0. Now at the first falling gauge if you see, then the input is low. That means the output of the flip-flop will also remain low. And it will remain in this state until the next falling gauge. Now once again at the next falling gauge if you see, then the input becomes high. So since the input is high, so the output will also become high. And it will remain in this state until the next falling gauge. So in between the two falling gauges, even if the input level changes, then also this flip-flop will not respond to that input level change. And at the next clock transition if you see, then the input becomes low. That means now the output of the flip-flop. will also become low. So overall this is the output of this negative edge triggered flip-flop. So as you can see for the same input and the clock signal, the gated latch and the flip-flop responds differently. Because this flip-flop is the edge sensitive while the latch is the level sensitive. So typically in the synchronous circuits, this flip-flop is used as the memory element. And in fact with the little modification, The gated latch can be used itself as the flip-flop. For example, if we add the clock transition circuit to this gated latch, then the same can be used as the flip-flop. So in the upcoming videos, we will also learn about that. But first, it is good to know the basic design of the latch. So these latches and flip-flops are implemented with the help of the logic gates. So in the next video, we will learn that How to design the transparent latch as well as the gated latch with the help of the logic gates. But I hope in this video you understood what is latch and flip-flop and what is the basic difference between the latch and the flip-flop. So if you have any question or suggestion, then do let me know here in the comment section below. If you like this video, hit the like button and subscribe the channel for more such videos.

which are used in the sequential circuits. That is latch and the flip-flop. Well, both the memory elements are able to store one bit of information. That means their output can be either 0 or 1. And since they have the two stable states, so they are also known as the bistable multivibrator. So in this video, let us understand what is latch and flip-flop and what is the basic difference between two of them.

So first of all, Let's start with the latch. So this latch responds to the input level change immediately. For example, let's say initially the input of this latch is equal to 1. And based on that, the stored value in the latch is equal to 1. Now suddenly, if the input level changes to 0, then the latch will also immediately respond to that input level change.

And based on that change, it will also change the output stage. So basically it is the asynchronous type of memory element. So this type of latch which immediately responds to the change in the input are called transparent latch.

Now there is another type of latch which becomes transparent based on the control input. So this latches are known as the gated latch. So as you can see this gated latch also has enable input. So when this enable input is high then this latch is transparent to the input. That means when this enable input is high, then the latch responds to the change in the input immediately.

And when this enable input is low, then even if the input changes, then it does not respond to that input change. And in that case, it retains its previous state. Now when we apply the periodic clock signal to this enable input, then the same gated latch can be used as the synchronous memory element. Because now This latch will respond to the input when the clock signal is high. And it will remain in its previous state when this clock signal is low.

So as you can see, basically it is sensitive to the clock signal level. But during this on time of the clock, if the input level changes, then it will respond to that change immediately. So let us understand the working of this gated latch with the help of the timing diagram.

So let's see. Here we have one gated latch and the clock signal is applied as the enable input. So here the signal which is shown in the blue color is our clock signal.

And that signal is applied at the enable input. So as you know this gated latch will become transparent when the clock signal is high. Or in other words when this enable input is high. So as you can see during the on time of this clock signal when the enable input is high, then the output of the latch is same as the input signal.

And after that, when this enable input becomes low, then even if the input signal changes, then also this latch will not respond to that input change. And as you can see, it is retaining its previous state. So in this case, during the off time, it will remain 0. Now once again, during the on time of the clock, when the enable input becomes high, then once again, the output will follow the input signal. So as you can see, during this time, this output is following the input signal.

And once again, during the OFF time of the clock signal, it will retain its previous state. So as you can see, during this OFF time, the input is going from HIGH to LOW. But still, this latch will not respond to that input change. And it will retain its previous state. Now once again, it will become transparent to the input.

when the clock signal is high. Or in other words, once again when the enable input is high. So at that time, since the input is low, so the output will also become low.

So this is the output of this gated latch. And as you can see, when this periodic clock pulse is applied at the enable input, then this gated latch will become level sensitive memory element. That means it will become transparent when this clock signal is high. On the other end, If you see the flip-flop, then it also has clock input. And it responds to the input only at the clock transition.

That means the flip-flop is the edge-triggered memory element. On the other end, if you see the latch, then it is the level-triggered memory element. Now this flip-flop can respond to the input either at the rising edge or the falling edge of the clock signal. So if it responds to the input at the rising edge, then it is called as the positive edge-triggered flip-flop. On the other end, if it responds to the input at the falling edge of the clock, then it is called as the negative edge-triggered flip-flop.

So, through the timing diagram, let us understand how this edge triggered flip-flop behaves to the input level changes. And first, let us take the case of the positive edge triggered flip-flop. So here, the same signal which we have applied to the gated latch is also applied to the flip-flop.

And this signal which is shown in the blue color is our clock signal. So since the flip-flop is the edge triggered flip-flop, so it will respond to the input at the rising edge of the clock. And here we are assuming that at the clock transition, the flip-flop follows the input signal.

That means at the clock transition, if the input is high, then the output of the flip-flop is also high. And if the input is low, then the output of the flip-flop will also become low. So based on that assumption, let us see what will be the output of this flip-flop. So as you can see, at the first rising edge, the input is high.

That means the output will also become high. But now, the flip-flop will respond to the input at the next rising gauge. And till that, it will retain its previous stage. That means in this case, until the next rising gauge, it will remain high.

That means up to this point, the output of the flip-flop will remain high. Now once again, at the next rising gauge, the input is once again high. That means during the next clock transition also.

the output will remain high. And it will remain high until the next clock transition. So in between, even if the input level changes, then also it will not respond to that input level change.

So now at the next clock transition, since the input becomes low, so the output will also become low. And it will remain low till the next clock transition. So as you can see, this is the output of this positive edge triggered flip-flop.

Similarly, for the same inputs, let's see the output of this negative edge triggered flip-flop. So this negative edge triggered flip-flop will respond to the input at the falling gauge. So till the first falling gauge, the output of the flip-flop will remain 0. Now at the first falling gauge if you see, then the input is low. That means the output of the flip-flop will also remain low. And it will remain in this state until the next falling gauge.

Now once again at the next falling gauge if you see, then the input becomes high. So since the input is high, so the output will also become high. And it will remain in this state until the next falling gauge.

So in between the two falling gauges, even if the input level changes, then also this flip-flop will not respond to that input level change. And at the next clock transition if you see, then the input becomes low. That means now the output of the flip-flop. will also become low. So overall this is the output of this negative edge triggered flip-flop.

So as you can see for the same input and the clock signal, the gated latch and the flip-flop responds differently. Because this flip-flop is the edge sensitive while the latch is the level sensitive. So typically in the synchronous circuits, this flip-flop is used as the memory element. And in fact with the little modification, The gated latch can be used itself as the flip-flop.

For example, if we add the clock transition circuit to this gated latch, then the same can be used as the flip-flop. So in the upcoming videos, we will also learn about that. But first, it is good to know the basic design of the latch.

So these latches and flip-flops are implemented with the help of the logic gates. So in the next video, we will learn that How to design the transparent latch as well as the gated latch with the help of the logic gates. But I hope in this video you understood what is latch and flip-flop and what is the basic difference between the latch and the flip-flop. So if you have any question or suggestion, then do let me know here in the comment section below. If you like this video, hit the like button and subscribe the channel for more such videos.

Transcript for:Understanding Latches and Flip-Flops

Transcript for:
Understanding Latches and Flip-Flops