hi everyone and welcome to the course named digital design with very Rock so this will be the first module okay then there will be second module I hope you have watched the introduction video and the road map and the course culum all those things I've explained in the introduction video so make sure you watch that video and there I have discussed about the syllabus so today we will start with the module one with the lecture zero where I will introduce you to verilog why very log is required and like what actually what is a bigger picture in digital design what are we doing okay so obviously we will not discuss about coding in the first few lectures like one two lectures then I will come to the coding before that we have to make a ground workor make a foundation the reasoning behind the need of readlock then obviously we'll go to coding and trust me whatever you will learn right you'll learn everything crystal clear and everything reasoning for everything will be clear to you so let's first discuss about the evolution of digital design so digital design is the process of creating Electronics primarily using digital circuits okay what are digital circuits like zeros and one right which operate on zero and one just like your computer your mobile everything any Electronic Component works on zeros and ones okay it focuses on designing systems such as processor memory units and communication systems okay so like I I I hope this is a very very famous uh picture I think this is from the B Laboratories where like they were building some super computer like which was not able to process much uh but the computer was so much bulkier I think it was around 1960s or something like that but today if I show you something if uh any of you guys have are Tech Enthusiast or if you know about Apple so like this is a few years back they released their chip named M2 Apple M2 right in m to previous L we had so many bulky things everything was separate Ram was separate processor was separate uh storage was separate then IO was separate everything was separate this M2 right M2 Chip which Apple actually built it had everything inside it it follows the arm architecture don't worry if you know don't know this technical terms that's totally fine for the students who know this I'm just explaining you because the interest may be more risen due to this fact right this M2 Chip okay this is the Apple silicon inside it we have 15.8 like it can do 15.8 operations per second okay it has 24 GB of RAM like it is very small okay it has 20 billion transistor that is the most important fact that is interest to us because we design anything with transistors right in in an Electronics domain we design anything with transistors so it has 20 billion transistors now of course you are not mad I also not mad How can I design anything with 20 billion transistors there has to be a method there has to be automation tool so exactly very loog also is a one of the one of the small thing that comes in the whole design flow for the automation obviously we cannot design anything with 20 billion transistor right of of course we can design but manually we can we cannot there need needs to be a automation tool because if we go into transistor level and place each transistor by hand okay then we have to take care of the like uh saturation levels okay whether the transistor is operating properly on active region or not okay so we have to take account of all of that all of that but there has to be automation tool that we'll discuss so that is what we do we make few abstractions okay because initially what we used to do around 1978 we used to design our circuit with transistors we just placed a p and Mos like that we should design our circuit then we move to schematic entry uh so I will show you I will tell you about each level slowly so the transistor level which is here is the lowest level dealing with individual transistors and connections so their gate drain connections Source connections all those things individually we connect this was around 1980s after 1980s we move to gate level abstraction design abstraction where we us should design our circuit with logical Gates we inside logical Gates of course there are transistors the and gate will be made with simos transistors and or get anything I hope you know all this so uh but we didn't use to uh take care of the individual transistor level connections we just used to take care of the gate level connections like and gate output will be connected to the next circuit wire okay like that this was in the schematic entry that was also a bit on the higher level so then we move to register transistor level what is register transistor level Reg transistor level focuses on data transfer between registers and functional blocks using Hardware okay so registers are actually on the higher level registers are made with Gates as well and with few sequential blocks as well okay so then we uh what we do is we Define the next cycle value depending on the currentc so this right used to use the sequential logic previously we used to build everything with uh current logic like this and right they don't have any cycle they don't have any uh like uh sequential logic to them right I cannot Define a next state equation if you have studied Digital Electronics you'll understand this so these gate level right only used only are used to uh like design the circuit depending on the current state okay but this right RTL we can design the circuit depending on the current state and on the next state that was the most important thing okay and transist levels what we do like basically in transistor level right we have to decide whether the next transistor will be on or off in in that particular state right but that is very tedious for us to decide that's why we moved on to this and then we moved on the moved on to the higher level of abstraction okay so this registor transistor level focuses on data transfer between resistors and functional blocks Hardware description languages like vog or PDL so this RTL is where we will code like this is the abstraction that we will do right because it has a very good blend of hardware and software okay so we will use Hardwares which can which can actually like we will Design logic depending on the current state and the next state and those Hardwares will then uh talk with the transistor that is like uh other thing that we don't take care we don't take care of the transistor we don't uh take care of the gates we just uh decide what type of registers to place and obviously registers is not only register there are many things as well which I will discuss don't worry about it but for now just understand that we will code our whatever we do right we will we will be will be in this level register transistor register transfer level okay then the next level comes that is even higher level of abstraction as I move down right the level of abstraction becomes higher now why does the level of abstraction become higher because the more lower like the more higher level of abstractions you go right the more further away you move from the hardware so sometimes there needs to be a good balance because of course you want to have a control over the hardware as well what type of Hardware you want to use if you automate everything then maybe the CPU have has chosen a optimized Hardware but maybe that is not properly optimized okay then you have to decide what kind of Hardware to choose yeah sorry for the noise so in gate level modeling right so not modeling gate level abstraction we actually cannot store values and all those things in register level abstraction we can store values like if you have studied COA from me then you you might remember there is a like if I do write something like this right R3 is R2 minus R1 that means what I'm taking values from R2 taking values from R1 subtracting the two and then storing it in R3 so this is what we do in register level abstraction and that is why storage is very important we will understand this slowly then what is system level like system level is which combines the uh complete system and we don't code here in vog we don't do system level what is system level we don't take care of the hardware at all like C++ and python whenever you code in C++ or python do you consider okay I am writing AAL to B plus C which kind of Hardware will it use no in very log you have to think about that if I write AAL to B plus C then maybe it will Implement a Adder as a hardware okay in very long but in C and python right we don't think about that we just write a equals to B plus C that's it okay we don't think about the hardware so it is just on the highest level of abstraction it is further away on the hardware okay so we will use rthl because it is it what it does is it is a bridge between the hardware and the software so it glues the hardware and the software together and we need to have both we need to have a control over both of course as I mentioned 20 billion transistors are there I cannot each uh control the each transistor okay 20 billion transistor that's why some level of automation needs to be there but some level of control also needs to be there to the hardware so that's why very we use the very loock vlock is a glue between hardware and software of course there are many component between hardware and software one of those component is very long okay there are other components which I will not discuss here that is not in our syllabus as well for now okay so basically what the programmers do what the programmers do programmers code in C++ if you remember the C guys coding guys they code in C++ but someone right someone in C++ also what we do someone in C++ needs to convert to machine language because if you have like even if you have done some BC programming right you know that when you write a code in C++ okay language when you write a code in C++ like like in I now if you tell this to CPU will CPU understand no CPU just understands zeros and ones right CPU just understand zeros and ones so of course someone needs to convert it who converts assembler if you remember compiler assembler something like that okay compiler like both have different tasks but for now we just make them together because this is not the purpose just I'm explaining you so similarly in coding domain they have some converter right in our digital domain also we have some converter because we of course if we like let's say I want to design a counter okay I will not directly design it Hardware right that will be so much tedious what I will write I will write a code okay of a counter I will write a code of counter I will not explain the logic right now okay and that logic will be automatically synthesized to a hardware which we know okay so that level of automation we need to make so for that level right we do RTL coding register transistor level so we do RTL coding of a counter then our synthesis tool right synthesis tool synthesis tool convert converts this into Hardware okay so that is what we mean by synthesis tool now there are many types of syn synthesis tool if our RTL if our this RTL coding right is converted to gate level of abstraction okay then it is known as as logic synthesis why logic synthesis because gate is combinational logic right you are telling the combination logic that's why it is logic synthesis okay that's this is what our very loog will do very loog will do logic synthesis it will just convert your R code into very uh into uh gate level of abstraction now what does if I directly want to convert AR code to transistor level of ab abstraction that is very difficult to do transistor level of abstraction then this is known as physical uh like synthesis physical synthesis now we have tools for this which of course we will not discuss mainly so in very log what we do this is the most important portion okay sorry in very log what we do in very log we do this we do logic synthesis so in logic synthesis basically we convert our RTL that is register transist level code it has a logic okay uh AR to our gate level of abstraction that is what very log will do it it a it is a synthesizing tool we'll write our codl and vog will automatically synthesize in gate level of abstractions so let's come to the automation tool as I was discussing we have 20 billion transistors we have to automate few things so there came few automation tools electronic design automation also known as Eda tools Eda tools automate the design simulation and testing of electronic circuits making the design process faster and less er error if human is involved you know error will be there so we we will try to make our process as smooth and fast and error prone as possible okay less error prone as possible now what happened initially days we used to do manual design and test with bread boards if you have done bit of lab you will know what bread boards are we used to test those manually but after few days we came to the gate level design as shown in the gate level abstraction in gate level obstruction we introduce cat tools for schematic capture like kadence in Cadence right we can have a Blog okay like a hand or something something and that is used for schematic capture previously we used to do manual entry okay manual drawing the blocks and all those things that is very tedious next we came to articl design okay what articl design did it used Hardware descriptive languages such as Vlog and vhdl for design specification we even didn't have we didn't have to use Cadence we just directly coded our design let's say I want to build a counter I just directly coded a counter and in vog and few languages such as Hardware descriptive languages so this vog and vhdl are known as Hardware descriptive languages languages we'll study vog obviously what uh what does these languages do this convert our logic that is our RTL code to Hardware so it became simpler before it was like I have to I have to make a design entry although everything is not properly seen with the picture that's why we code it seeing the code and understanding the Cod code is easier okay so code gets converted into Hardware that is much much easier for us yeah sorry for the interruption there is too much background noise sometimes I have to have to cut the videos so as I was explaining what is s so system on chip so this apple right Apple M2 silicon whatever you've seen it is s so so what we do we Implement multiple uh functionalities in a single chip just like in this M2 right it has a ram it has a vram as well it has uh like uh uh GPU CPU CES everything it has Insight in this one single chip okay that's why it is called as system on chip so I hope you have understood this thing like now we do these kind of designs currently what our uh like advancement is we have so good automation tools we can Implement all those all those things in a single chip it helps why it helps because if if everything is in is in a a single shape right then there is no delay between the data data transfer the GPU or CPU can directly transfer data very fast manner so that's why we want to build everything uniformly in a single chip okay there are many more Advantage which of course is out of the scope of this course so I will not discuss about that so of course like I will tell you basic things about digital circuits I hope you have already studied Digital Electronics from us okay so what does digital circuits do digital circuits basically manipulate the binary data 01 using the high voltage and low voltage levels very simple right only two voltage levels we have zero and one they perform computations and make logical uh decisions based on the inputs so if I'm giving some if I have orate if I giving it one one input right output will be one if I have a norget if I'm giving one one input out output will be zero so like this so that is what digital circuits work so this is digital circuits now what are combination circuits so combination circuits produce out puts based solely on their current inputs and they do not retain any past States okay just take example of few combination blocks like adders multiplexers decoders encoders these are all what these are all gate level abstractions okay they don't take care of the previous state just they take care of the current state if you have studied sequential C sorry Digital Electronics fromers you will understand the difference Okay so these are few examples and what we do is we Define the desired output what output we need to get we use the truth t to establish the relationship between the inputs and the outputs then we simplify using the bolean algebra or kmap okay so uh this right whenever we do do these kind of things we use gate level of modeling that I will explain later on don't worry about it but this basic thing you know obviously about combinational circuits in sequential circuits what we do we have like we can store information as well sequential circuits have memory elements so this comes to the RTL level of abstraction meaning the desired outputs depend on both the current inputs and previous States because it has memory elements so it can store the previous States and obviously current input will be given from the input itself so the output will depend on the current input and the previous outputs okay previous input sorry what are the components of a sequential circuit it has flip-flops like d TP flip flop JK Sr flip flop registers counters okay what is the working mechanism working mechanism very is simple like it will have some clock signal which synchronizes and the state changes it will have a feedback loop obviously that feedbacks the previous values okay to retain the past values what are the applications memory systems control units communication protocols Etc there are tens hundreds thousands billions of applications everything uses sequential circuits okay so like this just a Blog diagram this is just example these things you know that's why I'm not giving too much emphasis on this you already know about this because you have already studied the digital electronics formers the third one is again interesting thing that is FSM of course don't worry we'll code all these three we'll codee all these three okay what is FSM FSM are mathematical model used to design sequential circuits they help in managing complex State transitions like if uh currently I'm at a present State depending on the input and the present State maybe I will go to this state this state or other state there can be multiple States okay so that is what FSM does I hope you have learned this so uh basically what we to do we have to code our code will depend right our code code will depend code will depend on the uh on few specific condition okay next state next state will depend on specific conditions like if I am at this position then the next state will be this if I'm at this position then the next state will be this this okay so don't worry we will code all these things you don't have to worry about this at all but just giving you overview what what circuits we'll design first we'll design combinational blocks then we'll design sequential blocks then we'll design finite State machines okay so what are the components of a system first is States represent the various condition of the system let's say like um uh like let's say uh human right I can be hungry I can be sleepy I can be lazy or something like that my character State current state is I'm hungry because I haven't ate for 6 hours that's why I'm very very hungry so depending on the previous state because I was I haven't ate for many hours I'm hungry okay so that that can be a state okay then transition so if I'm hungry then what I will do I will eat the food I will take a food from the fridge and I will eat the food so transition is I'm going to the fridge and taking out the food I'm going to the fridge and taking out the food what is the output output logic is I'm eating the food something like that okay just giving you example don't worry we'll do this FSM at the end this will be that at the module two okay so example of a FSM is a vending machine it States can be ideal accepting coin or dispensing item so like if a vending machine is there if if you know about vending machine you can put like you can First Press what you want like I want a cold drink or a milk I will I will press that with the buttons then the vending machine will show that input 10 Rupees so I will input the 10 Rupees and then the vending machine will open the door and automatically give out the object okay so that is what we do here as well so like it has three states either it will be idle nothing has is getting done or it it is in the state where it will accept the coin or it is in the state for dispensing the items okay like basically giving out this milk so transitions based on the coin input and the item selected if I give it a 10 Rupees coin then obviously it will give milk Caron if I give it a 20 rupees like if I purchase a 20 rupees item then then it will give out a 20 rupees item that is the transition and uh dispense output is the dispense item or return change because let's say I want this milk it milk is 10 Rupees I have given it 20 rupees so vending machine is smart so it will give out the milk and it will give out the change as well because I I have given it extra 10 Rupees so it will give out the change of 10 Rupees so it will be total like it will give out 10 Rupees as well as a return and the milk carton as well okay so these are the few States okay so basically uh these are the few things that we will do with ar coding AR coding is much much more deeper because basically right here in AR coding uh like this right this is also done with the sequential logic only because sequential logic also has some storage and all those things so this can be done with sequential loging so Artic coding right this is what combination circuits is what like data is here XY it is Flowing throughout this path and getting to the output okay there is no storage or something so this kind of circuits are also known as data path circuits because I'm giving some input here and the data is propagating to the output okay now uh next is here as well I'm giving it some input and at the end I'm getting some output through the path of course I'm taking into account the initial previous States as well okay so this is what this is also known as data path and this FSM right is actually known as a controller why controller because it has lot of logic depending on the current state depending on each States output input all those things it has lot lot of logic so FSM has lot of logic so what we say is that's why it is a controller because it controls right it controls the state input output logic transition all those things that's why it is it is bit complex don't worry we'll discuss about this in the last few chapters so basically what I want I want to come to the conclusion is that AR coding right has everything article coding has data path as well Plus controller it has everything okay but it is not important for you just telling you a overview what is Artic coding this will when you'll go to a job right there you will understand about Artic coding mode for now just understand basics of V loock that's it nothing else you you don't need to understand anything else just wanted to give you overview that AR coding involves combinational blocks sequential blocks and FSM only these three blocks these three types of blocks we have except this right we don't have anything else okay so this is actually not that important this P I can remove okay so now let's come to the a bit of vsi domain so what is vs domain I already have explained about digital circuits so let's understand the development of vsi doain vsi is what very large scale integration refers to the process of creating integrated circuits IC by combining thousands to millions of transistors onto a single chip like as shown in the example of Apple M2 Chip there are billions of inside so obviously we have developed vsi uh first it was microprocessor then we developed memory chips now it is system on chips okay it is more efficient so we started with SSI what is SSI it is small scale integration whose year is 1964 previously like these are the like stats transistor SP chip logic gate SP chip it is very very lower okay then we came to medium scale integration which came into account like the year can be roughly wrong but around this time only It came it came in 1968 whose uh which has which has transistor perched a bit higher than the previous case if you see then the logic gate perch also in increased right and of course we developed few complex circuits like multiplexes decoders counters next we came to large scale integration which was developed in 1971 where transistors per Shi were increased even more like you can see right the development is 20 times more something like that 20 to 40 times more logic gates per chips also increased and we develop microprocessors around this time then we came to very large scale integration vsi which we got to know today like which we currently are using and obviously we have moved to this as well but we use this one as well okay which was founded in 1980 the transition pip raised very high level logic gates also raised and we developed Advanced microprocessors memory chips and E6 what is ASC Asic is application specific chip or application specific integrated circuit IC application application specific IIs that is what we mean by A6 okay so uh like we will come to this as well I will explain you a bit of A6 because knowing as6 is also important because few companies hire as6 Engineers you have to know what is as6 actually so I will tell you about that as well then we came to ultra large scale integration which are like the this is the architecture which our modern CPUs gpus all those things use like the Apple M2 right so you can see the stats so this is bit about the V domain now we will discuss about Coss complimentary Moss metal oxide transistor okay uh because you already know about SOS because you have studied digital elonics forers why we use SOS what is the reason for using seos SOS is a widely used technology for Designing integrated circuits that is also known as ICS due to it low power consumption high performance high and high integration capabilities it can be integrated with other circuits okay that's why so that's why we use SOS SOS circuits are a combination of P type and N type mosit P type is at the top p m and n MOS is as the bottom generally it is symmetric s circuit is symmetrical about the uh middle basically cannot say basically in the bottom we'll have all inos in the top a of all pmos uh uh to implement logic functions so like one by one I will go through the uh advantages of a seos First Advantage is very obvious it has low power consumption why SOS circuits consume only Power only during switching and almost no power in a static State when inputs and outputs are stable why it only consumes power only switching first of all let me say why it does not consume any power when it is in the static State when when it is in the static state right we know our gate current IG right is almost very low very low almost equalent to zero so to turn on on or off the device right basically I have to apply some voltage here right so as the gate current is very low VG will be some finite value VG into 0 will be zero right so then the power is zero that's why it is it has no power but while turning it on obviously there will be some transient there is some mosab and something like that some current will flow okay so during switching there will be some current but in uh stable states there will not be any current at all so IG is zero right that's why it has no current so this property makes simos ideal for battery power devices like smartphones and uh laptops because we don't have we have power constraints on laptops and smartphones right because battery capacity is limited that's why next reason is the fully restored logic levels SOS Ur that the output voltage levels are fully restored to the supply voltage levels okay what do I mean by this so if there is logic one right it will pull up to High plus VD and fully Resto logic levels if it is logic zero it will pull down to ground but few other circuits right they are they always don't do do this they always don't behave like this they always don't restore full logic levels they will not go to plus 5 volts or Z volts they can be sometimes they can vary right sometimes they will go plus 7 Volts for high for high I'm talking Plus 8 volts plus6 volts something like that and for low as well sometimes they will go 43 it may happen so they are really really not that ideal to use because they are not going too much zero or too much one right we need fully restored levels because in digital what we do mainly in digital we only use zeros and ones to identify zeros and ones better we have to have either very high value or very low value because even if there is signal degradation it ensures reliable oper operation right that is what is WR in the N line even if there's some signal issue right still I am able to identify that it will be high or low that is what we need to do okay next come to this seos compliment metal oxide semiconductor um sorry this is the full form basically third point is on off times are similar so um as it is symmetric right the on of times will be almost similar there will be bit of difference but we will Design our pm and N Moos such that the on of times are similar why because when you turn on right when you turn it on when you make it high then what happens then actually sorry when you make it high right then n MOS turns on N MOS turns on right I hope you know basic MOS Coss so if n MOS turns on so this output Z will be pulled down due to the due to the nmos so the pull down is happening due to the nmos and when this x is zero the pmos turns on if the PS turns on the pull up happens due to the posos okay so I will say pull down due to nmos and pull up due to poos okay pull down Pull up happens due to pmos andos now what you have to identify is that uh they are two different so if they have different switching characteristics obviously it is pulling it down right there will be some time delay so if the two different transistors are not balanced properly there will be different like pull down time time so initially it was let's say high okay initially let say it was high then it take it took this much amount of time T1 to pull it down right let's say initially it was low it take it took this much amount of time T2 to pull it up so if T1 and T2 are not same right there will be problems if obviously we want everything to Symmetry and I I will not go to everything like in detail but we need similar rise time and fall time so rise time and fall time should be same so what we do I will write here so as to make rise time and for Time same we adjust our height uh sorry W Val ratio okay we cannot adjust L actually we don't have like control over the L but we we will adjust the width of pamos and invas okay so to make it symmetrical so uh although they are almost symmetrical but we can adjust we have the we have the control to adjust over the rise and fall time okay that's why this is very good then High integration capacity High integration capability simos technology supports High transistor density basically many transistors can be put inside very small amount of space enabling millions of or billions of transistors to be fabricated on a single chip now if this is the property right then there is very less distance to send the data from one point to another point if there is less distance that means it will be more more faster so that's why we have high integration capability so high performance Sim operate efficiently at high speeds making them suitably application requiring fast processing such such as microprocessor and digital signal processing so we know camos is a very very fast object we can operate in at a clock frequency of gahz okay so that's why it is very suitable for us we can turn it on and off at very very high speed so on and on and off can happen on off can happen very frequently the simos will not get damaged okay so that's why switching speed is very good for SOS basic switching things I hope you know okay so yeah that was basically it and why is why does it like if it has high density right then what we can do basically while fabrication we can package them very close while fabrication while fabrication we can package them very close okay and if you package them very close then data transfer time will have lesser amount of DeLay So that is the advantage of these kind of things I hope you have understood this point right so yeah that was basically it about uh uh about the cosos transistor okay so now let's discuss about technology like few important uh terms I want to discuss okay few important terms I want to discuss okay so uh first is technology what does technology mean in semiconductor it is basically the minimum feature size so if you remember this M2 right here if I see somewhere uh have they written it okay yeah here this they have written this right what is this they they're telling they're telling that it is second generation 5 nanometer technology what does it mean what does this 5 nanometer mean this 5 nanom nanometer actually means the length of the transistor here I written right l so L is the like w by L ratio if you remember remember solving the trans right where L is the length of the like length of the transistor basically the channel length Channel length correct so this is what we mean by technology the minimum F size refers to the smallest physical dimension of a structure such as the transition gate or interconnect line that can be fabricated on a semiconductor chip it is a critical parameter that defines the capability and limitations of manufacturing process the smaller it is the less power it will consume that's why we we are reducing this the more density it will be yeah sorry for the interruption so as I was saying that like this is what our length is uh this determines the scaling of transistors which which in turn uh defines the performance power and integration density the more lower the length Channel length is the more transistors I can fit in same area so I will have more transistors more processing power so obviously we want to lower the length but there is a limitation to it right we cannot reduce the length infinitely but we are progressing so initially we were here at 10 micrometers around 10 micrometers here right around 1980s Now we move to nanot technology around 2000 right so like we are reducing our length will reduce with the graph so we are on a very fast pace we are reducing our transist transistor size very fast so it will only help us it will give us more processing power more transistors will be able to fit in the same area so that's why okay so like why like I I have told you why integration is so much important previously also I have telling you that integration is very important why the integration of millions or billions of transistors onto a single chip as enabled by vsi technology has re revolutionized modern Electronics okay so why because we we have more processing power more transistors will be able to fit in the same space obviously then more process processing power will be there that is what is written over here next is less area if I want to have the same processing power now it will take me less area lower amount of area right so if the overall area has reduced the space will be reduced the uh like power consumption will also be reduced due to that next is higher speed integration reduces the distance between the components right the length has reduced so the distance between the components has reduced the physical length has reduced physical distance has reduced speed equals to Distance by time time is same distance has reduced so uh sorry speed equal to Distance by time now distance like my speed is same speed is equals to Distance by time right my speed is same same like uh electron flowing speed is same okay my distance has reduced so what will happen to time time will also be reduced right because time is distance into distance divide by speed if the speed of electrons is same and the distance has reduced obviously time will reduce it will take me lesser amount of time for a data to flow from trans one to trans transistor 2 so definitely that will be only helpful to me okay that's why the third Point higher speed okay and portability the smaller the devices the easier I can Port like I can uh take that device in some other place in some other areas okay that's why the term portability is here next is smaller Integrated Systems enable the development of lightweight and portable devices okay like that is the point improve reliability integration reduces the number of interconnections like uh to the outside Source okay if there is a failure in the outside Source then the reliability will be reduced but as the number of Integrations has been reduced because multiple chips will be inside the same uh structure only so it will be more and more reliable okay so this here right one thing I forgot to mention low power consumption obviously you understand because of course less idea low power consumption why because there will be less cable loss why less cable loss because to interconnect each transistor right I have to I have to connect them with cables if the cable length has reduced obviously the distance for the electron to travel has reduced so the loss will also be reduced as mentioned here shorter interconnect distance and optimize power management okay so like these are the few points that you should know okay so okay one few topics have been repeated here these okay these are have been repeated I need to delete these things repeated twice okay here I so now few more important points although this is not that important this will not be asked in interview but you should know the whole flow like basic idea you should have like how does a vsi process happen because sometimes in interview the interviewer can ask if you know don't tell them by hand you know this if they ask then you can start talking about it that I have studied a bit about this okay so I will discuss about the design flow just overview I'll give you overview what is a ASC design flow Asic design flow is application specific specific integrated circuit design flow okay uh it is a structured process to develop a custom chip for a specific application so what is a design so to develop a chip that is what I'm discussing so this is the overview first we have a design spec right how fast you want your ADC okay what is the clock frequency what is the uh inl DNL what is the accuracy how much SNR you want SNR means noise signal noise ratio how much performance you want how much speed you want okay how much data you you should be able to store on that particular chip all those things will be here decided from the design specifics specifications designers will decide this right once designer decide a specific then they go to the behavioral description basically they will not directly go into the coding they will first understand in the higher level how they can design that that is what WR over here design specification like functionality signal processing control logic speed power and obviously they will decide which technology they want to use 5 nanometer technology 7 Nom technology like that constraints like obviously this is very very important constraint like budget how much money they have to build the chip right how much should it cost because they have to sell it on to the customers so customer like they have to build a chip that such that the customer should be uh enticed by that chip price to Performance ratio manufacturing timelines how fast I want that so all these things things right all these things okay number of also number of how many inputs it should have how many outputs it should have okay Power all those things I have discussed like that right so this is all what design team this is not just the design team which decide design team talks with the customers with their desired customers as well what the customers want according to those customers they will say hey I want a highspeed ADC something like that customers will say so first they decide how my product should be this is what the designers decide okay they discuss back and forth with the customer then they come to a specification they write down the specification next is they come to the this behavioral description what is this behavioral description this uh is known as the architecturing architecture is develop a high level architecture to make the design specification like this is a common uh microprocessor architecture right so what in architecture what they do they divide the bigger problems into smaller ones to smaller the similar let's say I have to design a 4 is to One Max what I will say is I don't know how to design a 4 is one Mar but I know how to design a 2 is one Mar so I will Design two 2 is one marks and and then interconnect those because I hope you know that you can design a 4 is to1 marks with two 2 is1 marks okay so dividing our bigger problems to smaller one so the partitioning the system into modules like I will divide the responsibilities you decide the control unit you decide the uh GPU you decide the CPU of course every a single uh uh person cannot decide right partitioning the like the responsibilities basically for M2 Chip there is a GPU there is a CPU there is a ram there is a uh there are other things as well right like memory storage all those things so I have partitioned the responsibilities and now I will develop modules for CPU modu for GPU then they will be reusable why we want to uh make modules because modules are reusable and this I will come to later on why reusability is very very important because once you have built a module right when the next person will come and work like he or she will Design the CPU he can directly start with the previous modu of course we need to make a few changes because the specs of the new chip will be different but the changes will not be that much drastic okay the changes will not be that much drastic we can use the modules okay now defining data flow and control flow like how the data will flow from the input to Output all those things will be defined in the behavioral model selecting algorithms and Hardware software tradeoffs as I told you right if I can build a MX 4 is to one MX in many ways one of the way is 2 is to one marks okay so I have selected 2 is to one marks as a hardware for the 4 is to one marks okay you can design something else as well you can design something else as well okay so all these things will be desided in the architectural that is here in the beh behavioral description now I will come to the r coding in AR coding what we do we implement the design at the register transistor level using Hardware description languages like very log or vhdl Okay so this is a AR code basically this is a very log code whatever we have decided in the behavi level we code it in R level okay to describe them in individual modules we Define the data path control signal clock and we ensure the modularity and readability of the code okay we code it we code it now after coding right this code then our very log converts this code into Hardware but of course what we do is once we code this right in uh Hardware then we come to the uh verification we verify the AR functionality that is the fourth point we verify the AR functionality so objective is to ensure that the arle design meets the specifications through simulation and testing what does it include it includes like uh functional verification code coverage formal verification so what are these basically we also have few tools tools for this we have few tools what are those tools those tools are system very lock very lock is what it converts the RT code into Hardware now system VAR log is what system VAR log is used for verification whatever we have coded are those correct or not basically let's say I have coded coded a highspeed ADC so I have designed it for SNR of 30 DBS so when I'm verifying it whether the SNR is 30 DBS or not or is it it is higher than that so that means whatever I have designed that is not good enough I have to design something else so that's why you can see there is a loop back here AR functional verified I'll verify if it is not matching with my design specs then again I will come to the behavioral description if it is not matching with my current specs or ar description whichever one is wrong whichever one whichever uh whichever uh step I was wrong I will rewrite that step okay that's why there is a loop back here if it is verified then I will then I can directly go to rtl2 logic okay R2 logic synthesis I will explain about that so there are few tools like system V then obviously there are simulation tools right what are the simulation tools simulation tools simulation tools like uh matlb okay I was just checking the sound whether there is some noise or not so we can use these tools first there is known as functional verification what does functional verification measure it verifies the logic correctness using test benches okay using test benches is verifies the logic correctness so basically any bugs we have in the code in the logic that it will verify functional means functionality is wrong like it is supposed to be a ADC analog or digital converter but it is not properly working that means the functionality is wrong next is code coverage ensure all design design paths are tested like in the circuit Hardware all the paths should be test tested there are many processes that like different companies use to ensure there is proper code coverage that whatever Hardware I have made all the paths all those path should be tested even if one of the path is wrong right then ultimately at the final uh uh what do you say production of the chip something will go wrong okay then there is formal verification mathematically prove design correctness and against the specification okay this right this doesn't check the spec Ms this checks the functionality if I have designed a MX then it should be able to select any four lines correct I don't check how is the strength of the signal or all of that all that is checked in the formal verification after like functionality is checked right then we check like whether the spec is getting met met or not basically the output SNR how is output SNR how is the uh how is the what do you say how is the inl is the D and all those things after that after this happens right then we'll go to this synthesis this whole step right this whole thing is also known as HDL design synthesis this portion is known as HDL design capture we design it we put in the schematic entry all those things but we actually not convert it into Hardware just design capture now we are synthesizing it to it Hardware that's why it is known as HDL design synthesis okay so here we synthesize convert the article code into gate level net list using Sy syn synthesis tools like vog and other things map the high level artical constructs using the technology specific Logics in your synthesizing tool There Will Be Few specific things right okay so that that is what it map optimize for power and area performance generate reports to validate the timing and resource allocation and utilization all those things it will do just don't have to go too much in depth of this just try to understand the steps okay just try to understand the steps Okay so actually this part one is common for uh most synthesis okay so basically this right I I write here so steps this AGD like for most cases this first step is always common but this last few steps right implementation this can be a bit different so I will not discuss about this currently so we write here that desile uh this right this design capture or design flow is almost same design capture is similar steps in design capture almost similar in everywhere okay but from synthesis onwards the steps will change okay that's why I will not discuss about those uh steps right I will ignore those steps for now because just I I wanted to give you a basic overview that's it nothing else just a basic overview okay so like this is what a H HDL design synthesis tool does because if I have a code right like this I will not explain you what this code is I also don't know just basically what it does HL code converts this code into Hardware okay I will I'll just zoom it out it will just convert this code into a hardware now there will be some inputs right this is the input let's say this is the input these are the all the inputs these are all the inputs and outputs like here there will be output as well okay don't have to worry about this code we'll understand this code and the interconnections right is decided by this code this interconnections are also known as data path okay so in the VAR of code I will give it some inputs code will be given some inputs okay inputs like uh the synthesis not the Val code sorry the synthesis tool what inputs I get give to the synthesis tool after giving it this code I will give it some constraint that the power must be less than 100 wat something like that okay the speed must be more than this clock frequency must be this okay give it some constraint of course I will give it the Artic code I'm talking about the synthesis tools synthesis tools so what are these constraints these constraints are used to optimize for what I want to design optimize for like let's say area my area must be this speed power and more okay then Artic code of course I will give then there is standard cell library in the synthesis tool there will be some standard s library or I can give my own library that use this type type of Nate which has delay of one Nan if uh the synthesis tool has some uh like if the synthesis tool has some kind of uh like what do you say some kind of Nate but it has five nanc delay I don't want to use that okay I don't want to use that so I will give it some standard cell library as well which have all the information of what it has information of the logic gates which of course it will Implement on all few other Hardwares few standard Hardwares okay so that is what the synthesis tool will do so there are many synthesis tools like synopsis uses or something okay they convert this so we will not discuss about that right now so finally in the output right output what I will get in the output I will get a net list from the synthesis tool and what kind of Hardware it has to use this is the output this is the output and the input of course I have told you this I will give and in the output as well they will show you show me the data path and all those things okay so that is what a syn synthesizing tool just then after this like this is also a very very important step for designing a chip known as design for testability DFT this is not that signals systems topic DFT right this is design for testability so DFT the objective is to incorporate testing features into the design to ensure manufacturability and defect detects sorry detect defects because functional anality you have checked okay all those things you have checked but now once you try to manufacturer there can be some manufacturing defects some problems will be there okay uh so basically right this DFT is a very very sought after job because this checking this right is very very difficult you have to minimize the processing time let's say Somewhere In Your Design you're using a three input nangate three input Nate or anate whatever you want to say you're using a three input andate now how many inputs I need to give to check this three input n manufactur defect like I have to check all every single Hardware in DFT right every single Hardware how many inputs how many total combinations 0 1 so 2 three combinations I need to get give to this and get and check the outputs so total I need to check eight different cases eight different cases now can can I somehow minimize this can I somehow minimize this so that is what it that is the task of a DFT engineer okay to check this properly can I somehow minimize this okay so we have to design a test plan so that I can minimize this like you have to define a logic so I will not go into that right now but you have to design a logic now eight different cases is fine but let's say I have a chip that has th000 inputs and I have to check all the th000 inputs so how many different cases I will have it will be two days to th000 which will be a lot okay so I don't want that right of course chip can have th000 inputs right it has th000 resistors I have to check all of them even if one of them is wrong that means what my chip is not working properly it is not functioning properly so I have to discard that chip so that's why designing this kind of functional anality is very very important okay so there can be process defects like if you are designing in some particular technology there can be few problems with that so you will not use that okay there can be some open circuit short circuit fault in your path okay so you have to add additional Hardware to check defects so you have to add this additional Hardware to check defects so there should be built-in self test test or some scans I will not go too much in depth here just giving you an idea so that you understand what is the job of a vs engineer there are many things in vs right not just simple Electronics okay developing analog chips not that there are many things so all these things are there I will not go too much in depth then you have your timing analysis also known as St right so this is where you decide your clock frequency is correct or not okay so in all these steps right you go back and forth if you see this particular thing right you go back and forth to your initial step right why because you have to discuss with the designer as well hey uh we did some DFT test this is not actually what we are getting we are not getting our desired performance according to your design so we may have to change few things okay so this is like very B thing I hope you know what is uh like setup time whole time you have to do check whether whether there is no stda violation or not all the things okay you have to verify clock domain Crossing CDC for multiple clock designs if I have multiple clocks are they synchronized or not properly so all these things you have to design so this right is for layout guys so I will not discuss much about these things this is after all these things have been done right finally functionality have been checked design has been checked testing has been done now you come to the layout part where you actually start the layout of the chip which will then go to the manufacturing okay all these things you back go back and forth between layout placement okay because there can be many optimizations right if you place the chip just before here just before this particular uh position here here okay there can be many things I will not discuss about that few basic thumb rule there are like DRC DRC is what DRC DRC is design rule check just like a handbook that if you are using this technology then you must place the chips like this or like this okay so design rule check so few basic things you have that's it that's it okay next is the formal verification power estimation I will not discuss like this like all these steps are going back and forth something like that you can discuss with your designer back and forth so I have given you a basic overview about the design flow not that important but still to get a good idea because in interview sometimes they will they may ask you design flow you not you may not know everything because you are on B level that's why I give you overview now let's discuss about Hardware descriptive languages why are they needed okay so for years programming language like for and Pascal C were primarily used for sequential programs what is sequential program sequential program means sequential execution of programs sequential execution execution what do I mean by sequential execution so in sequential execution let's say I have this code right uh a plus b like C = A + B E = to D + f in SE equational program this will happen first then this will happen like let's take example for C right in C this will like this line will be executed first then this line but what we needed similarly in the field of digital design there was a growing demand for standardized language to describe the digital circuits what were those digital circuits like uh like because digital circuits what they used to do they used to work concurrently so this led the development of hdls also known as Hardware description languages which enable designers to model the concurrent processes inherent in the hardware system so if the same code is written in verilog or HDL right Hardware descriptive language D Plus then what it will do both of this will happen parall because I will have a Adder two adders I will have okay two adders I will have input will be a here input will be DF this will be the output this will be C this will be F this will be e okay so this right this is not like this will happen first or this will happen first I have separate hardware for this so they will happen concurrently so there's a huge huge difference between normal C language and your loog so don't get confused your Hardware descriptive language right hdls are happen on Parallel execution execution okay they don't happen sequentially they happen parall two of the most prominent hdls are vog HDL and vhdl which gain probability we will study vog HDL very HDL was introduced by gway Design automation vdl was developed by uh D DRP defense advanc resarch project agency so this is not important this is important okay so yeah that is about that um like very log HDL so initially while hdms become uh became widely adopted for logical verification designers still had to manually convert the hgl based design into schematic basically the uh synthesis right showing gate interconnections they have to manually interconnect this process changed dramatically with Advent of logic synthesis in late 1980s designers could now describe circuits at the register transistor level okay basically they can design Define at the reg trans level using HDL then there will be some uh like synthesiz tools so RL focuses on how data flows between registers like this right AB is here how is data flowing through a full then I'm getting the output like this focuses on this and how the system processes the data how does it process there I have a Adder sometimes I will subtractor then I will have a multiply something like that okay then logic synthesis tools automatically generate the necessary gate level details like here right I have only written this is a full add inside this full what type of logic gates are there and gate or gate I don't care logic synthesis tool will automatically do the Gen will automatically generate this gate level details okay and interconnections from Artic description whatever description I've given here it will automatically do that I will say I have a full letter it automatically inside the full letter it will understand what kind of uh gate level things it has to do okay that is what the logic synthesis tools do okay instead of manual placing Gates designer could focus on High level functionality like the logic and all those things and the manual thing will be automated leaving the detailed implementation to the synthesis tool synthesis tool will be automatically do the detailed implementation so what is the role of vog vog is used to write like we can write we can Define our circuits all those things in vog code we can Sim simp simulate the functionality we can synthesize into gate level atet list by using synthesis tool also we can perform placement and routing which we don't do but we can perform this as well and we can validate and test using physical implementation as well so these are all the design flow like this is what is the role of vlock in the design flow right it is used here in these things in these three things in these three things very log is used the last two things can also be done but we generally avoid doing that we do it with some other tools okay advantages of very concise and efficient for large design support for Behavior structure we'll understand what is behavior structure what is uh like gate level modeling stru level modeling we'll understand that don't worry about it then there is strong integration between the Eda tools Eda which I told you is the design automation automation tool right so uh it has integration with those Eda tools as well okay so that's it basically for this lecture this lecture was mainly theoretical we did not do any coding or something because I want to get a good foundation why are we doing what we are doing okay then obviously we'll understand the codee and from the next lecture onwards will understand about the different design methodologies in V also we'll Implement a half adder with different levels ofra abstractions okay thank you for watching and I hope to see you in the next lecture until then Happy learning