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Understanding SR Latch in Digital Electronics

Aug 30, 2024

Lecture 119: Digital Electronics - SR Latch

Overview of Sequential Circuits

  • Difference between combinational and sequential circuits is the presence of a memory block in sequential circuits.
  • Memory element stores past outputs, aiming to store single bit numbers (0 or 1).

Key Storage Element: Latch

  • Basic storage element is called a latch.
  • Focus of this lecture is on the SR latch.
  • Types of SR Latch:
    • NOR SR Latch
    • NAND SR Latch

Functionality of SR Latch

  • Inputs: S (Set) and R (Reset).
    • S = 1 sets output Q to 1.
    • R = 1 resets output Q to 0.

Important Characteristics of SR Latch

  • SR latch operates similarly to a door latch:
    • In a door latch, once closed, the door cannot let anything in or out.
    • In an SR latch, changing inputs can change stored data.
  • Importance of using a clock to control data storage (to be explained in future presentations).

Truth Table for NOR Gate

  • For two inputs A and B, the output Y for a NOR gate:
    • 0 0 = 1
    • 0 1 = 0
    • 1 0 = 0
    • 1 1 = 0

Case Analysis of SR Latch

Case 1: S = 0, R = 1

  • Q = 0, Q' = 1 (Q complement).
    • Reset state: outputs are complementary.

Memory State

  • When S = 0 and R = 0 (inputs removed), the outputs remain the same (stored state).
  • Proven that outputs store previous states.

Case 2: S = 1, R = 0

  • Q = 1, Q' = 0.
    • Set state: outputs are complementary.
  • When inputs are removed, the outputs (1, 0) remain stored.

Case 3: S = 1, R = 1 (Not Used State)

  • Q = Q' = 0.
    • Contradictory situation.
    • Leads to undefined behavior (not allowed).
  • If inputs are removed (S = 0, R = 0), conflicting outputs arise.

Summary Table of SR Latch States

SRQQ'Description
00Q_prevQ'_prevMemory State
0101Reset State
1010Set State
11Not UsedNot UsedUndefined State

NAND SR Latch

  • Shift from NOR to NAND gates.
  • Key changes: S and R are now set and reset in the NAND configuration.
  • Truth table: Similar steps followed as NOR gate.
    • 0 0 for S and R results in memory state.
    • If S = 0, R = 1 then Q = 1, Q' = 0, etc.

Conclusion

  • Understanding SR latch is critical for grasping future topics like flip-flops, counters, and registers.
  • Questions are encouraged for clarification.
  • Importance of understanding the material for success in the course.