Basic Electronics: Clamper and Voltage Doubler Circuits

Introduction

• Discussing clamper circuits
• Focus on negative level shift circuits
• Combination of clamper and peak detector to create a voltage doubler circuit

Clamper Circuit Overview

• New clamper circuit with reversed diode polarity
• Ideal diode model: V_on = 0 volts
• Input voltage: V_s(t) = V_m * sin(ωt) where V_m = 5 volts
  • V_s varies from +5V to -5V*

Key Observations

1. Capacitor Charging:
   • When diode conducts, capacitor charges instantaneously.
   • V_c = V_s when diode conducts (since R_on is small).
2. Capacitor Voltage Behavior:
   • V_c can only increase.
   • Maximum V_c is V_m (5 volts). After reaching max, it remains constant.
   • Output voltage: V_o(t) = V_s - V_m (negative level shift).

Graph Analysis

• Initial condition: V_c is 0.
• As V_s increases, diode conducts and V_c increases, coinciding with V_s.
• Once V_c reaches V_m, the output shifts downward from V_s by V_m.

Clamper with Non-Ideal Diode (V_on = 0.7V)

• Maximum V_c now is V_m - V_on = 4.3 volts.
• Output now shifts:
  • V_o(t) = V_s - (V_m - V_on)
  • V_o(t) = V_s - 4.3 volts.
• Output voltage clamps at 0.7 volts.

Voltage Doubler Circuit

• Combination of clamper (positive level shift) and peak detector.
• Input voltage: Sinusoidal from -V_m to +V_m.
• Output of positive clamper shifts from 0 to 2V_m.
• Peak detector detects peak: Output is a DC voltage of 2V_m.
  • Achieves voltage doubling from sinusoidal input.

Circuit Implementation

• Basic setup:
  • C1 and D1 = Positive clamper
  • D2 and C2 = Peak detector

Waveform Analysis

• For ideal diodes (V_on = 0V):
  • Input (Blue), Clamped (Green), Output (Pink).
  • Output builds up to 2V_m over a few cycles.
• For non-ideal diodes (V_on = 0.7V):
  • Output shifts to 2V_m - 1.4V due to diode drops.

Circuit with Two Diodes

• Similar to clamper, but has both charging and discharging paths for the capacitor.

Problem Statement

• Input waveform from -V_m to +V_m (e.g., -10V to +10V).
• High interval (t1) and low interval (t2); with diode I-V characteristics.
• Find V_o(t) in steady state.

Key Time Constants

• Charging: τ1 = R1 * C.
• Discharging: τ2 = R2 * C.
• Both τ1 and τ2 are much larger than t (steady state assumption).

Steady State Behavior

• Capacitor voltage (V_c) is nearly constant in steady state due to large time constants.
• Output voltage: V_o(t) = V_i(t) - V_c.

Example Calculation

• Input: V_m = 10V, t1 = 0.25ms, t2 = 0.75ms, R1 = 5k, R2 = 10k, C = 10μF.
• Confirm conditions: R1 * C = 50ms, R2 * C = 100ms (both much larger than t1 and t2).
• Steady state value of V_c: ~ -2V.
• Final output: V_o = V_i + 1.86V (positive shift of V_i).

Summary

• Explored clamper and peak detector circuits for voltage doubling.
• Analyzed diode circuits using steady-state assumptions and charge conservation.
• Next class: Diodes in rectification (AC to DC conversion).

Key Terms

• Clamper
• Peak Detector
• Voltage Doubler
• Diode I-V Characteristics
• Steady State Analysis