[Music] hey guys welcome back to my channel electronics media today in this video i am going to explain about the reset domain crossing and its techniques in my previous video i have explained about the basics of the resettlement crossing like what is reset recovery what is the set removal and the definition of the rdc if you haven't watched that video please go and check it out i have given the link in the description box so let's get started so uh before we proceed with the reset domain crossing techniques i would like to explain what is the set domain crossing one more time so reset domain crossing is nothing but if you see when the data is going from one reset boundary to another reset boundary here if you see we have two resets uh reset n1 and set n2 so the data what that is launch from this flip flop one so it's getting captured in the fluff by the flip flop too so if you see the data is moving from this uh reset one domain that is over here and then to the reset uh two so now when this happens so there is a possibility of uh that the destination flop can go into a meta stable state because of that the the your chip may fail i would like to explain this concept with the help of the waveform so now uh assume this is your clock okay so we have this clock okay now this is reset n1 okay so now any uh this reset n1 is basically we have this is something like this it's uh asserted okay uh it's a d asserted over here this is a active law and now we have this set n2 so this is something like this okay it's there now what happens is uh now assume the reset n2 which is out of the result that means it's the reset ds added and similarly the second one so now the data is propagating from the flip flop one to flock to all is good okay so now what's happening if the reset n1 goes uh if it gets asserted okay so because the reset assertion is asynchronous right because this is asynchronous said if it gets asserted somewhere in the uh near this setup or us or the reset removal or recovery time window right so then what happens if it gets asserted like this something like this right so then what happens this is anyway out of reset the q uh the initial assume that the q one okay this is my q one okay this is q one and q two so this q one initially it was one okay now since it's asserted okay it went to the zero value okay uh means the output the reset value of this flop is a zero so it was one and it went back to zero so now what happens is since the clock is the same okay now the d2 will be exactly equal to the q one but the q two what happens is that since this sig this uh you know or d one input right so this is a d two into this is the d two input so it is changing from one to zero uh at the active edge of this clock so if the q2 might be sampling this a wrong way okay so it can be either zero or one and here or else it will become we can call it as a meta stable state so so what if it goes into a meta stable state so then the q2 if it propagates further to some other block right so then this also can go into meta stable state and you may you may not you you may have the undesired outputs so your chip might fail okay your chip might fail so because of this we need to ensure that all of the you know set domain crossings are also you know checked properly so now unlike you know cdc this uh reset domain crossing is very difficult to catch because this is this can have uh with a regular you know cdc tools so it's difficult to catch this and also this you know uh reset domain crossing requires a system level analysis like how these each of the resets are you know getting asserted how these results are getting reasserted what is the nature of the resets all of these you know things needs to be taken into account so there are various techniques through which you can fix this you know reset domain crossing uh issues so i would like to explain all of these like you know three or four concepts so then you will understand how can we fix all of this you know over you know resettlement crossing violations so the first method is by the rtl fix so uh what is what do you mean by rtl tech tail fix so basically if you analyze this right so what happens is this d1 the q1 is going to the uh d2 for the second flop flip flop so what we will do is since the reset is you know coming from the reset one domain and to the reset two domain so okay so this data is going from one domain to another domain what we will do is we'll break this down and what we'll do is we'll insert a synchronizer in the path okay so this is a standard double synchronizer okay two stage [Music] synchronizer what we will do is uh once it's inserted what happens is now the reset of this you know what we will give is we will give the same result as the reset two so for this double synchronizer now what happens thus q1 is coming on the reset n1 but it is going to the double synchronizer or the two-stage synchronizer once uh it hits this double synchronizer so this double synchronizer can go into a meta stable state okay momentarily okay for some time uh for the that's the first stage and the second stage will ensure that you know the data whatever we are getting which will be proper okay so it's a free from the meta stable state and then it can go to the you know the our uh other all of the flip flops or the other modules so with a by inserting this uh you know two-stage synchronizer we can resolve this you know uh reset domain crossing issue already have explained about the double synchronizer how they work and on so if you want to go and check it out or i will give the link in the description also so you can you know understand better how this double synchronizer will reduce the meta stable issue now the second thing is about the reset ordering so this is a important aspect so reset ordering is at the system level so you have to understand how these results are getting asserted and the dsetted now uh if you uh uh uh like you know if you see this right like your reset twenty one and they say ten two right so initially the reset n2 was de-asserted and then reset n1 got asserted if that happens then we will see this meta stable issue but what we will do is in the reset ordering we will ensure that okay now when the reset n1 is getting asserted okay so that time we will ensure that the second reset is also asserted okay it's also asserted so what do you mean by this so now uh so now what we will do is here i'll just put this okay now this is a reset n1 initially uh uh it was reasserted and then it went it was asserted now what happened in the reset n2 it was initially like this it's it was there so now we will see if this edge falls in the uh you know the percentage of the clock so right then uh we will see the meta stable issue but what we will do is for the reset n2 we will keep it in the asserted state that means the the second block so second module or the receiving module is still in the you know in the in the reset state it's in the reset state so what happens is if it is in the still in the reset state now even if the reset n1 is getting asserted right so then what happens by even uh the data can change over here okay it can go into meta the data can be toggling okay at the active edge of the clock but still we will not be able to you know sample that because we are in a reset state so then what happens is once the data becomes the reset is stable right so the reset and one is stable then only we will you know release this result n2 so by this ordering what happens is now we are ensuring that the destination is still under the reset state when the source is getting uh you know uh our reset is getting asserted so by this we will reduce this you know meta stable issue okay so now uh coming to the um uh one more fix so that is uh it's a basically rtl fix itself it's kind of a uh you know clock gating technique so what we will do is so in the clock getting technique what we will do here um instead of this is a it's connected like this okay and [Music] this is the clock is which is going okay now what happened when the reset n1 is getting asserted what we will do is we will that during that time we will have a clock gating logic over here clock gating logic so this will ensure when the reset is getting you know asserted ok this is the gated clock so the this clock will be gated off so that means when the clock is getted off the second module so we will not be able to sample the data so that time this will not go under a meta stable condition and when the reset is completely it's again reasserted so that or if it's asserted right so then what happens um if it's once it becomes stable so then we can you know release this clock so that you can sample the value properly so this is one of the method where we can fix this reset domain crossing now the third method is by adding the waivers or constraints so adding the waivers or constraints is you are telling the tool that sometimes these violations are ok to have because we are taking care of the reset ordering so that means you are giving the constraint to the tool saying that this is my reset router so the in the if you uh go through the spyglass uh you know documentation you will understand that the how to provide this you know rdc constraint so it's something like a reset order something like this if you need to mention and this is my r1 to r2 something like this some you know format is there so you can go through that so where what we are doing we are going to mention that r1 is also this is a reset n1 and reset n2 so first this uh reset oh sorry okay this is at n2 and the set n1 so we are telling the tool that this will be uh you know the the reset two will be asserted first and then the reset and one so so by this what we are telling the two do not populate the any violations associated with this and there is a one more way so there is a waiver so this is a you know we will not uh it's this is um you know by where once the violations are popped up we are going to waive it off manually but this is a tedious process and also it's kind of a risky because you have to analyze each and every violation and then only you have to waive it and sometimes what happens if you change the names or if you the path gets changed right so then the new violations may pop up and the old waivers may not be applicable so this is a tedious process so we'll try it over this but you can give this you know a reset order uh you know constraint and also there is a constraint called reset filter path where you can mention like you know from reset n1 to reset n2 if there are any violations you can you know suppress those so that's something called a reset filter path so this is also one of the constraint okay so through which you can suppress the all the violations so this is all about the reset domain crossing i hope this information is useful and please do let me know if you have any queries in the comment section i'll be happy to help thank you [Music] you