Lecture Notes: Multicycle Processor Design and Pipelining

Introduction

• Continuation of multicycle processor design from previous lecture.
• Discussion on microarchitecture of a simple MIPS processor.
• Single cycle processor design is not ideal due to violations of fundamental principles.
• Today’s focus: Full multicycle processor design for a subset of MIPS ISA, followed by pipelining.
• Extra credit assignment due April 1st.

Multicycle Processor Design

Overview

• Multicycle design allows each instruction to take time based on its requirements, not by the worst-case instruction.
• Multiple clock cycles can be used to process instructions, allowing different instructions to take different numbers of cycles.
• Clock cycle time is independent of instruction processing time.

State Machine Design

• Instructions processed via a finite state machine that sequences states and returns to the fetch state.
• Control signals are asserted per state, determining data path operations and next states.

Multicycle Design Goals

• Better critical path design, reduced clock cycle time.
• Optimization for common workloads and balanced design.
• Downsides: hardware and sequencing overhead, limited concurrency.

Multicycle Processor Construction

• Example: MIPS load word instruction.
  • Instruction divided into multiple stages: fetch, decode, address calculation, memory read, and write back.
• Store instruction builds upon load instruction design.
• R-type instructions: Similar process with ALU operations and using destination registers.
• Branch instructions require additional logic for target address and condition calculation.

Control Logic

• Control logic constructed for each stage, similar to single cycle design but executed state by state.
• Example of load word instruction flow through states.

Microprogrammed Control

• Concept introduced by Maurice Wilks; microprogramming involves sequencing between states using control signals.
• Control store holds microinstructions, acting like a small program.
• Enables easy extensibility of ISA and correction of hardware bugs via microcode updates.

Pipelining

Introduction to Pipelining

• Aim to improve throughput by allowing multiple instructions to be processed simultaneously.
• Instructions in different pipeline stages at the same time, increasing instruction throughput.
• Ideal pipelining: no dependencies, uniform partitioning of stages, no shared resources.

Pipelining Example

• Comparison of non-pipelined versus pipelined execution.
• Pipelined execution improves throughput but not the latency of individual instructions.

Pipeline Design

• Involves splitting the instruction processing cycle into distinct stages with pipeline registers in between.
• Example pipeline stages: fetch, decode, execute, memory access, write back.

Pipeline Hazards

• Hazards arise when there are dependencies between instructions or a resource conflict.
• Types of hazards include data hazards, control hazards, and structural hazards.

Control and Data Hazards

• Control signals are delayed to stages where needed, using pipeline registers.
• Handling hazards involves techniques like stalling, forwarding, and branch prediction.

Conclusion

• Pipelining greatly enhances throughput by overlapping instruction execution.
• Requires careful design to manage hazards and dependencies.
• Continues in the next lecture with more on pipelining and real-world processor designs.