Computer Architecture Lecture Notes (Final Lecture of the Semester)

Introduction

• Final computer architecture lecture of the semester.
• Focus on five research paper presentations.
• Topics include self-managing DRAM, row hammer, and SSD error mitigation.

Self-Managing DRAM

• Published: MICRO 2024
• Problem: Implementing new DRAM maintenance operations is complex and time-consuming.
• Goal: Simplify the process for implementing new maintenance operations.
• Key Idea: Modify DRAM interface to allow DRAM chips to reject memory accesses to regions under maintenance.
• Benefits: Performance and energy-efficient operations at small area cost.
• Implementation: Three in-DRAM maintenance mechanisms.

DRAM Interface Overview

• DRAM chip communicates with memory controller over DDRx interface.
• DRAM operations orchestrated by memory controller.
• Current interface is unidirectional and controlled by the memory controller.
• Error Modes: DRAM subject to errors necessitating maintenance mechanisms (e.g., periodic refresh).
• Barrier to Entry: Modifying standard is a lengthy process.

Proposed Solution

• Enable autonomous maintenance operations in DRAM chips.
• Simple interface change: allow DRAM chips to reject access commands.
• Benefits: Manufacturers can optimize architecture without exposing proprietary information.

Detailed Design

• Introduce lock regions and lock controller in DRAM banks.
• Steps to lock/unlock regions involve maintenance operations setting bits in a lock region vector.
• Memory Controller Interaction: Retry rejected commands at defined intervals.

Use Cases and Evaluation

• Implemented mechanisms: fixed rate refresh, deterministic row hammer protection, memory scrubbing.
• Evaluated performance and energy efficiency improvements.
• Significant speed-ups and energy savings observed.

BreakHammer

• Problem: Row hammer mitigations can lead to decreased bandwidth availability.
• Goal: Reduce performance overhead by throttling threats triggering row hammer solutions.
• Key Idea: Detect and slow down threats causing many row hammer preventive actions.

Mechanism Overview

• Observes row hammer preventive actions and attributes scores to hardware threads.
• Identifies and throttles suspect threads, reducing memory bandwidth usage.
• Implementation: Works with existing mitigation mechanisms like per and PRACK.

Evaluation and Results

• Reduces preventive actions and improves system performance under attack scenarios.
• Slight improvements even when no attack is present.

Sector DRAM

• Problem: Energy wastage due to coarse-grain data transfer and row activation.
• Goal: Develop a fine-grain, low-cost DRAM architecture.
• Key Ideas: Enable data transfers smaller than cache block size, activate small DRAM row portions.

Sector DRAM Design

• Use existing mat subdivision to enable sector activation.
• Modify DRAM I/O to allow variable burst length.

Performance Evaluation

• Substantial energy savings and performance improvements.
• Outperforms many existing fine-grain DRAM architectures.
• Small area overhead.

SSD Read Latency Mitigation

• Problem: Read retry leads to long latencies in SSDs.
• Goal: Reduce latency of read retry operations.

Proposed Solutions

• Pipeline Read Retry (PR Square): Overlaps read retry steps using cache read commands.
• Adaptive Read Retry (AR Square): Explores reducing read timing parameters using ECC margin.

Results

• Significant reduction in SSD response time (up to 42% improvement).
• Effective at both read and write dominant workloads.

Conclusion

• The presentations covered significant advancements in DRAM and SSD technology, focusing on reducing latency and energy consumption while enhancing system performance and reliability.
• Open-source resources for further exploration and research.