8086 Microprocessor Architecture

Jul 24, 2025

Overview

This lecture explains the architecture (block diagram) of the 8086 microprocessor, covering its major structural units, registers, address calculation, and pipelining advantages.

8086 Microprocessor Basics

  • 8086 is a 16-bit microprocessor; it processes 16 bits of data at a time.
  • It features a 16-bit data bus and a 20-bit address bus, allowing access to 1 MB physical memory.

Main Architectural Components

  • The architecture is divided into two main units: Bus Interface Unit (BIU) and Execution Unit (EU).
  • BIU is responsible for instruction fetching and address manipulation, while EU handles instruction execution.

Bus Interface Unit (BIU)

  • BIU contains segment registers, adder circuit, and a 6-byte instruction queue (FIFO policy).
  • It fetches instructions from memory and stores them in the instruction queue for the EU.

Segmentation and Registers

  • Memory is divided into four segments: Code, Stack, Data, and Extra.
  • Segment registers: CS (Code Segment), SS (Stack Segment), DS (Data Segment), ES (Extra Segment) - all 16 bits.
  • Instruction Pointer (IP) holds the offset address within code segment.
  • Offset registers: SP (Stack Pointer), BP (Base Pointer), SI (Source Index), DI (Destination Index).
  • Formula for physical address: Physical Address = (Segment Address × 10h) + Offset.

Execution Unit (EU)

  • EU includes control system, Arithmetic Logic Unit (ALU), general purpose registers, offset registers, and flags.
  • EU retrieves instructions from the instruction queue, decodes, and executes them using ALU.
  • General purpose registers: AX, BX, CX, DX; each split into high (H) and low (L) 8-bit parts.

ALU and Data Processing

  • ALU performs arithmetic, logic, shift, data transfer, and control operations.
  • The accumulator (AX) is the default operand source for ALU operations.
  • Results are stored back to registers, then to memory via BIU.

Flags and Operands

  • Flags indicate status or results of operations (e.g., carry, zero, overflow).
  • Operand sources may include immediate values, registers, or memory.

Pipelining Concept

  • Architecture split enables pipelining: BIU fetches instructions while EU executes instructions, increasing processing speed.
  • Unlike previous processors (e.g., 8085), 8086 can overlap instruction fetch with execution.

Key Terms & Definitions

  • BIU (Bus Interface Unit) — Handles instruction fetch and address generation.
  • EU (Execution Unit) — Executes instructions and processes data.
  • Segment Register — Holds base address of a memory segment.
  • Physical Address — Actual memory address used by the processor.
  • ALU (Arithmetic Logic Unit) — Performs arithmetic and logic operations.
  • Pipelining — Technique allowing overlapping instruction fetch and execution for faster processing.

Action Items / Next Steps

  • Review "register organization" for more details on register functions.
  • Study the different types of flags in the 8086 processor.