ARM Cortex-A Series Programmer's Guide for ARMv7-A

ARM Processor Modes and Registers

General Purpose Registers

• ARM architecture provides sixteen 32-bit general purpose registers (R0-R15).
• R0-R14: General purpose data storage.
• R15: Program counter - changes as core executes instructions.
• CPSR and SPSR (Saved Program Status Register) are accessible by software.

Register Banking

• Register banking involves different physical storage locations for registers depending on the mode of execution.
• Shaded registers in diagrams indicate banked registers.
• Banked registers use physically distinct storage, generally accessible only in specific modes.

Register Functionality

• Low Registers (R0-R7): Share the same physical storage across modes.
• High Registers (R8-R12): Banked for FIQ mode, using different storage locations.
• R13 (Stack Pointer): OS stack pointer; can be used for general purpose when not involved in stack operations.
• R14 (Link Register): Holds return address from subroutine calls; can serve as a general purpose register.
• R15 (Program Counter): Holds the current program address; points ahead of the current instruction due to ARM's pipeline design.

Register Initialization

• Reset values of R0-R14 are unpredictable.
• Stack pointer (SP) must be initialized by boot code for each mode before stack operations.

Application Binary Interfaces

• AAPCS or AEABI: Standards specifying the use of general purpose registers to enable interoperability across different toolchains or programming languages.

Program Status Registers

• CPSR: Current Program Status Register accessible by software.
• SPSR: Saved Program Status Register saved from the previously executed mode.
• ARM principles dictate using these registers to manage processor state and control program flow.

This summary covers the essential aspects of the ARM register set as outlined in the programmer's guide, focusing on their configuration, usage, and role in the ARM architecture.