Lecture 119: Digital Electronics - Latches

Key Concepts

• Sequential Circuits vs. Combinational Circuits
  • The main difference is the presence of a memory block in sequential circuits.
  • Memory elements are used to store past outputs (0 or 1).
  • Storing bits allows for multi-bit storage (e.g., 100, 101).

Latch Overview

• The basic storage element in sequential circuits is called a latch.
• Types of Latches:
  • SR Latch
    • Two types: NOR SR Latch and NAND SR Latch.

Latch Functionality

• Inputs:
  • S (Set): When S = 1, Q = 1
  • R (Reset): When R = 1, Q = 0
• Memory concept:
  • If S = 0 and R = 0, the latch retains its output (memory state).

Truth Table for NOR Gate

• Inputs: A and B
• Output: Y
  • Combinations:
    • 0 0 -> 1
    • 0 1 -> 0
    • 1 0 -> 0
    • 1 1 -> 0

Case Analysis for NOR SR Latch

1. Case 1: S = 0, R = 1

   • Q = 0, Q' (Q complement) = 1
   • Output: Reset state (memory maintained when inputs removed).

2. Case 2: S = 1, R = 0

   • Q = 1, Q' = 0
   • Output: Set state (memory maintained when inputs removed).

3. Case 3: S = 1, R = 1

   • Q = 0 and Q' = 0
   • Not allowed: leads to contradiction (Q must equal Q').
   • If S = 0 and R = 0, outputs are inconsistent.
   • Conclusion: S = 1 and R = 1 is not a valid state for SR Latch.

Summary for SR Latch States

| S | R | Q | Q' |
|---|---|---|----|
| 0 | 0 | Previous Output (Memory) | Previous Output' |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | Not Used | Not Used |

NAND SR Latch

• Similar structure as NOR SR Latch.
• Inputs change: Set and Reset are the same, but logical functions differ.
• In NAND Latch:
  • S = 0, R = 1 -> Q = 1
  • S = 1, R = 0 -> Q = 0
  • S = 0, R = 0 -> Not Used (memory state).
  • S = 1, R = 1 -> Valid memory state.

Final Notes

• Understanding the SR Latch is crucial for mastering sequential circuits like flip-flops, counters, and registers.
• Important to grasp the analysis of both NOR and NAND SR Latches thoroughly for future presentations.