D Flip-Flops and Transparent Latches

Jul 2, 2024

Lecture Notes: D Flip-Flops and Transparent Latches

Key Definitions

  • D Flip-Flop: A type of flip-flop that captures the value of the data input (D) based on the transitions of the clock signal.
    • Rising Edge D Flip-Flop: Captures input when the clock signal transitions from 0 to 1.
    • Falling Edge D Flip-Flop: Captures input when the clock signal transitions from 1 to 0.
  • Transparent Latch: A type of latch that passes the input to the output as long as the control signal (clock) is in a certain state.
    • Active High Latch: Passes input to output when the clock is high.
    • Active Low Latch: Passes input to output when the clock is low.

Truth Table Representation

  • Rising Edge: Often indicated with a small step up or an up arrow.
  • Falling Edge: Often indicated with a small step down or a down arrow.
  • These transitions indicate moments in time rather than steady-state levels of 0 or 1.

Timing Diagram

  • D Input Example: Random changes in D over time.
    • Drawing example with rising and falling transitions marked.
    • Indicates moments in time where D will influence the output depending on the type of flip-flop or latch.

Behavior of Different Circuits

Rising Edge D Flip-Flop

  • Q Output: Captures the value of D at each rising edge of the clock.
    • Values between rising edges remain constant.
    • Values before the first rising edge are typically unknown.
    • Notation often includes both logic 1 and 0 with transitions marked as 'X's.
  • Example:
    1. D = 1 at rising edge -> Q = 1 until next rising edge.
    2. D = 1 at rising edge -> Q remains 1.
    3. D = 0 at rising edge -> Q == 0 until next rising edge.
    4. Continue pattern.

Falling Edge D Flip-Flop

  • Q Output: Captures the value of D at each falling edge of the clock.
    • Values between falling edges remain constant.
  • Example:
    1. D = 0 at falling edge -> Q = 0 until next falling edge.
    2. D = 0 at falling edge -> Q remains 0.
    3. D = 1 at falling edge -> Q == 1 until next falling edge.
    4. Continue pattern.

Transparent Active High Latch

  • Q Output: Follows D when the clock is high.
    • Holds the last value of D when the clock goes low.
  • Example:
    1. Clock high: D changes, Q follows D.
    2. Clock low: Q holds last D value.

Transparent Active Low Latch

  • Q Output: Follows D when the clock is low.
    • Holds the last value of D when the clock goes high.
  • Example:
    1. Clock low: D changes, Q follows D.
    2. Clock high: Q holds last D value.

Summary

  • All these elements are types of memory devices.
  • Outputs (Q) depend on types of flip-flops (rising/falling edge) or latches (active high/low).
  • Real-world use cases and applications will be discussed in the next lesson.