Systematic Object Oriented Programming

Course Overview

• Example of converting a module-based response to a class-based test bench
• Course demonstrates conversion from a simple system module-based test bench to a class-based test bench
• Target Audience: Beginners in SystemVerilog
• Resources: Links to introductory courses and tutorials in the description

Problem Definition

• Model a DUT (Device Under Test) and a test bench
• Focus on AXI (Advanced eXtensible Interface) with a single interface (write address interface)
• AXI Interface Signals: ID, Address, Length, Valid and Ready
• Initialize signals starting with AW prefix
• Include Clock and Reset signals
• Introduce 'dummy DUT' if learning testbench coding without a real DUT

Step-by-Step Process

Writing an Interface and Dummy DUT

• Interface Definition: Use interface keyword
  • Name: xr_write_addr_interface
  • Signals: Clock, Reset, ID, Address, Length, Valid, Ready
  • Use Clock, Reset signals
  • Defined using interface and endinterface
  • Mod Ports define signal directions for Master and Slave

Writing Dummy DUT

• Simple Logic: Drive the Ready signal using a urandom function
• DUT acts as a Slave
• Always assign interface.ready to random values

Writing Test Bench Code (Module-Based)

• Define internal signals (Clock, Reset, number of transactions)
• Dummy DUT instantiation with necessary inputs
• Use tasks to structure the code cleanly:
  • init_signals: Initialize signal values
  • drive_transactions: Send random transactions
• Simulation: Assign values and display log messages using $display function
• Use EDA Playground for coding and simulation

Transition to Class-Based Test Bench

Transaction Class

• Class Definition: axi_txn
  • Data Members: id, length, and address
  • Use rand or randc for randomizable fields
  • Constructor: Initialize members
  • Constraints: length >= 1
• Methods:
  • copy: Deep copy for transaction objects
  • convert_to_string: Creates a formatted string with transaction info

Using Transaction Class in Testbench

• Simplified testbench.sv file
• Initialization and random value assignment in initial block
• Tasks like drive_transactions use the transaction object's values
• Helper methods for displaying transaction details

Full Class-Based Test Bench

SystemVerilog Class Architecture

• General Components:
  • Transaction Class
  • Generator Class
  • Driver Class
  • Mailbox for synchronization
• Mailbox: Used for communication between Generator and Driver
  • put function in Generator
  • get function in Driver

Generator Class

• Attributes:
  • Mailbox instance
  • Transaction count
• Methods:
  • Constructor to initialize mailbox
  • run task to generate transactions and place them in the mailbox

Driver Class

• Attributes:
  • Mailbox instance
  • Transaction count
  • Virtual Interface
• Methods:
  • Constructor to initialize mailbox and validate interface
  • run task to retrieve transactions from mailbox and drive DUT

Integration and Execution

• Top-level module connects all objects together
  • Instantiate generator, driver, and mailbox
  • Connect mailbox to generator and driver
  • Connect virtual interface in driver to the DUT's interface
• Synchronize tasks with fork...join to run generator and driver in parallel
• Finish simulation with $finish

Execution and Results

• Generated transactions appear as expected
• Display messages show transaction details from Generator and Driver

Summary

• Covered modeling and converting module-based test bench to class-based test bench
• Introduced Dummy DUT, Interfaces, and systematic transaction modeling
• Transitioned to class-based testbench step-by-step using Generator and Driver classes
• Resources for advanced topics and practices linked in the description
• Encouragement to subscribe and visit the SystemVerilog Academy website for more resources

Happy Learning! 🧑‍🎓