hardware description language is a computer-based language that is used to design the hardware of digital or analog systems in textual form one way to design digital systems is through the visual approach where you try to connect circuit diagrams using wires and the resulting design is what we call a schematic diagram however when circuit complexity increases it is harder to design the circuit using schematic diagrams and this is where we turn to textual computer language that concisely captures the details of the digital design the key advantage of using a textual form of design like a standardized hdl or hardware description language is that when you pass your circuit design to other engineers or designers they can easily understand it and edit it in an efficient manner when they want to edit your circuit they will just change a few lines of codes instead of disconnecting and connecting some wires here are some examples of different hardware description languages altera hardware description language or ahdl is an hdl developed by altera corporation and it is used for altera's complex programmable logic devices or cplds and field programmable gate arrays or fpgas just another hardware description language or jhdl is an hdl that allows you to build circuits using object oriented approach for example you can group logic gates into java objects etc etc vh sic hardware description language or vhdl is an hdl used to design digital and mixed signals like integrated circuits in contrast to verilog vhdl will require you to write more code for the same task that is about to be carried out in a way verilog is more compact than vhdl by the way vhs ic means very high speed integrated circuits we now turn to verilog verilog is an hdl that is based on the c language and it is used for modeling electronic systems another example of hdl is system very log system very log is just an enhanced version of verilog that has additional features like verification language object-oriented design etc in our class we will be using verilog because it is the most popular hdl that is used in the semiconductor industry to start the discussion let's familiarize ourselves with a few concepts used in verilog a verilog test bench or a test bench is just another verilog file that is used to test the timing and functionality of a module of a design we use a test bench to simulate and analyze designs without connecting a physical device like an fpga or practically speaking a test bench is just another code for you to test a very long code logic synthesis refers to the process of deriving a list of physical components and their connections from the model described by the hdl code this list of components and their connections is also called a netlist the logic of a module can be represented in any of these three varilog modeling style that i'm about to show you in gate level modeling the circuit is represented by specifying its logic gates and their interconnections in data flow modeling operators that act on binary operands are used to represent the logic of a circuit in behavioral modeling digital circuits are represented at a functional level here the designer only needs to know the algorithm of the circuit and the designer does not need to know the gate level design of the circuit let's now turn to verilog basic syntax when it comes to the basic syntax first of all verilog hdl is case sensitive in other words if you change one letter into an uppercase or lowercase letter then you now have a new variable and so on white spaces like spaces tabs and new lines are ignored keywords are lowercase when we say keywords these are words that have special meaning in verilog hdl in other words you cannot use them as variable names because they are reserved words in this language variable names must start with alphabetic character or an underscore in any programming language variable is just a container for values in addition system tasks and functions starts with dollar sign comments in verilog are similar to c language if you want to have one line comment use a double forward slash if you want to have multi-line comment use slash asterisk then the comment then asterisk slash comments are text that have no effect in the simulation in this demo i'll begin coding using the old version then i'll gradually transition to the new version in the succeeding uploads in verilog hdl a module is a fundamental unit that performs a specific function practically speaking a module is just a block of code enclosed between the keyword pair module and end module the keyword module is followed by the name of the module and if your module requires inputs and outputs the module name is followed by the list of input and output ports so we collectively call this a sport list and this port list is enclosed by parentheses each component of the port list is separated by commas the keyword module must always be terminated by a keyword and module if your module contains ports then you must tell how to use these ports and the following lines i'm declaring parts a b and c as inputs and ports d and e as outputs in other words i'm telling the computer that i will be using ports a b and c as inputs and ports d and e as outputs so just like the c language each statement in verilog is terminated with a semicolon when it comes to studying verilog hdl we will use icarus verilog platform because unlike other platforms icarus verilog does not force you to do registration in other words it doesn't let private companies harvest personal information from the users to install ecorus verilog or iverilog [Music] open your favorite web browser and type in ecaros verilog download the browser will recommend you an external link to the packages like the ones in blair.org but i prefer to open the original iverilog website so that you can still download the installer in case the external links changes its url so open this icarus.iverylog.com once you're in this website click this here link directly below this where is icarus very log text and once you click the link it will bring you to this ivery log installation guide scroll down until you reach installers if you're using windows choose ecorous varilog for windows click this link and it will bring you to blair.org go to download section and click the latest table release whatever that executable is your installer download will now begin i'll open the downloads folder and transfer the installer on the desktop to remind myself that i will delete it after the installation process right click the installer and run it as administrator because you will be installing it in your c drive after that the icarus verilog setup dialog box will open accept the agreement before clicking next note that it requires you to choose installation folder without spaces click next in my system it will be installed in c drive backslash ivery log folder i'll just click next make sure that install gtk wave checkbox is enabled to install gtk wave click next later i'll demonstrate the purpose of this gtk wave here you can modify the folder name of icarus verilog but i won't change the default name so i'll just click next i don't want to create a desktop icon because i want my desktop to be as clean as possible so i'll uncheck this one and click next then click install leave the add the executables directory to the path variable checked then click finish just to make sure that ivary log libraries are accessible when you use the terminal let's update the environment variable even though there's a prompt a while ago that the path variable is already updated so i'll go to the location of the executables in my system it is in the c drive iverilog bin i'll copy this path in the windows search bar type in system or control panel then click control panel click system and security then system then advance system settings click environment variables under user variables click new add variable name iverilog then paste the variable value which is the bin folder path then click ok click ok and then click ok and then close all these windows to check if ivary log is installed open windows terminal by typing windows terminal on the windows taskbar search bar and then click windows terminal in the terminal type iverilog v then hit enter to check the version of the installed ivery log if ivary log is successfully installed you'll see the version number you may now close the terminal let's now use an awesome text editor called vs code to facilitate our verilog coding to install vs code fire up your favorite web browser then type visual studio code then hit enter go to this first link code.visualstudio.com if you're using windows click this download for windows and your installer will download after downloading click open file to run the installer click run click i accept the agreement then click next i'll just choose the recommended bs code installation folder so i'll just click next i'll just choose this default shortcut folder so i'll just click next i will not change the default so i'll click next then click install i don't want to launch vs code for now so i will uncheck this then click finish we usually open vs code by typing visual studio code on the windows taskbar search bar and then clicking the vs code icon vs code can be used with many programming languages to customize vs code for verilog programming click this extensions button and type verilog you must be connected to the internet to do this when there are multiple options i usually choose the extension with the most number of downloads and with the highest reviews click this varilog hdl extension click install after installing the verilog extension click file option from the vs code menu bar preferences then settings collapse extensions and click verilog configuration find verilog linting linter then select iverilog after this go to file again then click save now that everything is in place let us explore verilog hdl by implementing a sample circuit like a half adder but before that let me open the executables that are created when we install verilog if you install it in the c drive of a windows operating system we can see the executables at the bin folder we can access these executables because we updated the windows path variable a while ago one of the most important executables here is the gtk wave so we run this application if we want to view the timing diagrams of our design next is the ivary log application and this application is used to compile the source files and finally we have this vvp executable and later we will run this because this serves as the simulation runtime engine now since my computer is already populated with lots of development software's i'll just create a folder here named ivary log underscore test so here i'll create the desktop a folder i vary log underscore test and then transfer this folder inside this bin folder this is just my personal preference because my documents folder is already cluttered so i'll just dump all my files here that are related to very log so i'll open this folder to begin our coding i'm going to create a file with an extension.v though that extension is just by convention but we will follow this convention to denote that our file is a very long file let me choose this first text document and then i'm going to name it as have underscore adder dot v this file is still a text file and not a very long file so i'm going to open my text editor which is the vs code click this windows search bar and then type visual studio and click this visual studio code and then drag and drop this file here note that if you see this file name have underscore adder that be that text this means that this file is still a text file let's try to save it as a verilog file so in this visual studio code or vs code text editor i'm going to click file save as and then i'm going to change the type as scroll down i'll choose very long okay and then save when we return to our folder i now have this v file so i'm going to delete this text file to avoid confusion so returning to our dot b file or verilog file with the file name have adder let me type a comment here to remind us that this is the module for half adder meaning to say this is not a test bench have other declaration saved in the file have adder that be i'm just writing this comment for demonstration purposes so i'm just going to increase the font size of this text editors so i'm going to click file preferences settings and then click the text editor and then click font so here the default is 14 i'm going to change this to 24 so that you can easily see the code hit enter then close the settings now i have a larger font next let us see the schematic diagram for a half adder plus its corresponding truth table so we will now begin coding this schematic diagram so we will enclose this in a module so type module notice that vs code has some intellisense or some autocomplete features because earlier we installed a plugin for verilog click space and then let's name this module as half adder based on this diagram it has inputs a and b so i'll just use small letter it doesn't really matter if it's caps capsular or not then sum and then an output of carry so in very log we terminate a statement with a semicolon enter to increase readability of your code i'm just going to indent it with four spaces or one tab one two three four i'm going to declare that the ports a b here are inputs a b then terminate it with a semicolon next the sum and carry here that will be passed on this module are actually output ports so i'm going to declare them i'm going to tell the compiler that these ports are used as output ports next i'm going to instantiate some gates or i'm going to create some virtual object for the gates to create our first gate which is an xor gate i'll type in xor and then the name of this gate let's just name this as x1 so what i'm doing here is i'm creating a virtual object a virtual gate and the name of that gate is x1 when you use primitive gates the first argument is the output so i'm going to type sum and then the remaining arguments refer to input so the inputs for x1 based on this diagram the inputs are a and b so i'm going to terminate this with a semicolon next i'm going to create or instantiate and gate with a name a1 so i'm going to type and for and gate and the name of this and gate is a1 we are naming these gates because sometimes in a schematic diagram or in a digital circuit you have multiple gates that's why it's important to name them the first argument or first set of arguments should refer to outputs in our case the output of this a1 gate is carry and the inputs are a and b so that's it we already created the module or the verilog hdl code for this half adder circuit so i'm going to end this module recall that a module must always be terminated by an end module keyword so ctrl s or click save file save next in order to test this code we will create a test bench code so here i'll just copy this file copy and then paste it in the same folder ctrl v i'm going to rename this copy as the same name as the module but at the end i'm going to include underscore tb which denotes that this is a test bench dot b so i'm going to drag this and drop it here on bs code i'm going to delete everything so for demonstration purposes i'll just include a comment here that this file is the test bench for half adder that be and this is saved in the file have underscore other underscore tb which means testbench.v so in our class we use this naming convention that if you want to create a test bench for a specific module you just name that testbench with the same name as the module name but include an underscore tb at the end so we will instantly know that it is a test bench and not a regular module click accent then include space the file of the module to be tested which is half underscore adder dot v so when you have this accent mark here for example accent include this means that it is a compiler directive meaning to say you will execute this line during compile time and during compile time you are actually telling the compiler that you have to include the contents of this file when you try to compile this test bench next we will again enclose the code for our test bench we in keyword pair module and module so i'm just going to type here module and then enter and module between this two keyword pair we will place our code for testing this half adder circuit so let's name this testbench as half underscore adder underscore db and since this doesn't require any inputs and outputs we don't have to include any ports here i'll just terminate this with semicolon in this test bench i must somehow be able to vary the values of the inputs so to do that i'm going to type here reg to denote that a and b are inputs according to some references reg means registers and this is understandable because as we all know a register is some digital element that can store a binary value like zero or one registers can be implemented in terms of flip flops or an array of flip flops or any other solid state components and as we all know we can vary the value of register so this is an appropriate name for a declaration for an input in a test bench next if we want to declare the output of the circuit in a test bench we use the keyword wire although in my opinion a proper name for this declaration is a probe because when you have a probe you're actually measuring a signal that comes from the outputs of a system so in my opinion probe is a better term than wire but then again in verilog when you want to tell the compiler that some variables are used as output you declare them as wires so again the outputs here are sum and carry after declaring the purpose of these variables which we will pass as arguments later we instantiate our module to be tested which is the half adder module so to do this type the name of the module which is in our case we named it as have underscore adder space then the name of the instance for example add one then we pass these variables a b sum and carry a b if this is an actual circuit this line of code means that we connect these test ports from our test circuit to the ports of the actual half adder circuit so i'm going to terminate this statement with a semicolon when we say instantiate we're actually creating a virtual object of this circuit in the memory of the computer next we create an initial block and the code inside this initial block is executed once during the entire simulation since we have a small circuit this initial block is enough to change the values of the registered inputs if i only have one statement then this keyword initial does not need to include begin and end meaning to say after this initial keyword and notice that autocompletes this initial block but if you have one line of statement you can just directly insert your code here but if you have multiple lines of code inside this initial block then you have to enclose this with a begin and end statement so for example begin and then end once you enter this bs code autocompletes the entire block so inside this begin and and block we will insert our code to change the values of this a and b so at the beginning we set the values of a and b to zero a equals zero and then b equals zero then after one second we replace their values with based on this through table zero and one so i'm going to place b with one and then after one second i'm going to change this with one zero i'll just copy this and paste one zero and then after one second i'll change the values to a equals one and b equals one so when you run this test bench apparently the registered variables here a and b will have different values but in order to view the timing diagram we have to dump this saved data because apparently when you change the values of a and b the values of sum and carry will also change as well and in order to record these changes we're going to dump these changes in this variable in a file and to do this let's try to put it inside this begin block also let's use the command dollar sign dump file whatever the changes are in this module we will save these changes in a file and we name this file as for example have other dot vcd i'll terminate this with semicolon dollar sign dump file is a command used to dump the changes in the values of the registers and wires in a file whose file name depends on the argument for example in our case we just name this file as half underscore adder that bcd vcd means value change dumped by default it will dump all the changes in this file but if we want to control which variables to save we use the command dollar sign dump bars it has two arguments the level and the module name or variable name so let's just put 0 here which means that we are dumping all the variables of the module and other variables instantiated by this top level module now the top level module that i'm going to indicate here is the module have adder db so that we can save the changes in these variables the argument here is directly read as a string so i'm going to drop this code and then i'm going to terminate this with a semicolon let's save this file ctrl s or click file then save to compile this test bench click this toggle panel here to display the terminal notice that the current directory or the default directory of this terminal is the home directory of the current user of this operating system but we need to access these files so i'm going to copy the current location of these files and then go back to my terminal and type cd which means change directory and then paste the directory of our files so i'll click enter i'm going to click clear just to remove some details of this terminal okay now i'm currently at the location of this file so i can directly compile them so to compile them i'll type i very log space minus o or the output the output will be named as let's just name it as have adder underscore tb but this time its file extension will be that vvp the source file to be compiled is half adder which is our test bench underscore tb dot v so click enter so when i return to this location or folder notice that a dot vbp file is created next i'm going to simulate this vbb file using the vvp command vbp command space then the name of this vbp file which is half adder underscore tv that bvp click enter if we return to this folder notice that a dot bcd file is created so this dot vcd file is the dump file that contains the changes in the outputs and inputs of this test bench so to view the timing diagram of this dump file open gtk wave so type gtk wave on the terminal and hit enter and we now have this a user interface for gtk web so to view this dump file click file up a new tab and then click the vcd file then click ok select have adder.tb and then click one signal from this dump file and then click ctrl a to select everything and then click insert so that they will be inserted in this signals panel and now the timing diagram are displayed for all the signals coming from our test bench so if i click in the middle of zero to one second so the initial values of a b is zero based on our truth table the carry and sum must be zero zero and this is correct next let me click between one second and two second and the values for a and b are set to zero and one and according to our truth table the carry and sum of our half other circuit must be 0 and 1 and our very long hdl code is consistent or correct and clicking between 2 seconds and 3 seconds the values for a and b are set to 1 and 0 and based on the simulation the resulting carry and sum is zero and one which is consistent with our truth table and finally clicking beyond three seconds the set values for a and b are one and one and based on our truth table the values of carry and sum must be 1 and 0 and if we try to match this with our simulation our simulation is correct which means that we have successfully implemented this circuit using the verilog hdl [Music] before we end this discussion let's look at another circuit that contains multiple gates and multiple wires to easily code this in verilog hdl we label each gates and netlist components for example we label the first or gate with o1 the first and gate with a1 the first not gate with n1 the second or gate with o2 and the second and gate with a2 when it comes to the wires we label this wire with w1 the second wire with w2 the third wire with w3 and the fourth wire with w4 so to implement it in verilog hdl i'm going to copy this half other dot v so that i'll automatically have a very log file and just rename this as for example sample underscore circuit then i'm going to drag and drop this on our vs code i'm going to delete everything so to implement this i'll start with module enter and let's just name this circuit as sample underscore circuit i'm going to put some port list here a b c d and e and an output of y i'm going to terminate this with a semicolon and then enter let's declare a b c d e ports as inputs a b c d e let's declare y as output and let's declare these wires w1 to 4 as wire next let's instantiate the first or gate so i'm going to type r and then the name of the or gate which is one and it has an output of w1 and inputs a and b next we instantiate the first and gate so i'm going to type and and then the name of the and gate is a1 it has an output of w2 and inputs c and d next let's instantiate the nut gate so i'm going to type not space the name of the nut gate is n1 the output of n1 is w3 and its input is w1 next i'm going to instantiate the second or gate so i'm going to type or space the name of the or gate is o2 and its output is w4 and its inputs are w3 and w2 finally i'm going to instantiate the second and gate so i'm going to type and space a2 its output is y and its inputs are w4 and e then i'm going to close this module by writing and module so to test this you're going to repeat the same process that i've shown you earlier and that's it don't forget to like this video subscribe to my youtube channel and hit the notification bell button for awesome updates thank you for watching