Lecture Notes: Pipeline Processor Design

Overview

• Focus on basics of pipeline processor design
• Handle data dependence and control dependence
• Continuation of issues with pipelining in following lectures

Review Reminder

• Review due April 1st, before the next lecture
• Covered: Multicycle micro architecture, pipeline design
• Recommended readings provided, especially H&H readings

Multicycle Processor Recap

• Discussed multicycle processor and finite state machine
• Highlighted issues of multicycle memory access
• Can improve with pipeline: execute different instructions in different stages

Pipelining Basics

• Pipelining: executing multiple instructions concurrently in different stages
• Improves throughput compared to multicycle processors
• Built a five-stage pipeline: Fetch, Decode, Execute, Memory access, Write back
• Need for pipeline registers to separate stages

Single-Cycle Microarchitecture

• Started design with a single cycle micro architecture
• No internal micro architectural registers
• Data path and control logic designed for single cycle

Pipeline Data Path Design

• Start with single cycle data path
• Decide how to break it down into stages
• Five-stage pipeline chosen (fetch, decode, execute, memory access, write back)
• Add pipeline registers to separate stages
• Propagate data signals to appropriate stages

Pipeline Control Logic

• Control signals: same as single cycle processor
• Propagate control signals to correct pipeline stage
• Example: Reg write signal should be asserted in the right-back stage

Handling Stalls

• Pipeline stalls: when pipeline stops moving
• Causes: Resource contention, dependencies, long latency operations
• Dependencies: Data dependencies (flow, anti, output), control dependencies

Data Dependencies

• Flow dependence: true data dependence (read after write)
• Anti-dependence: write after read on the same register
• Output dependence: write after write on the same register
• Flow dependencies cause stalls, anti and output dependencies easier to handle

Handling Data Dependencies

• Detect and wait until data is available
• Data forwarding: supply data directly from later stage
• Software-based interlocking vs. hardware-based interlocking

Control Dependencies

• Related to program counter
• Control flow instructions determine next fetch PC
• Branch prediction: always not taken, early branch resolution
• Accurate branch prediction reduces pipeline flushes

Conclusion

• Pipelining increases throughput but introduces complexities
• Dependence handling crucial for correct and efficient execution
• Branch prediction a key area for improving pipeline performance
• Future lectures: explore out-of-order execution and advanced pipelining techniques