Notes on IEEE Standard for Verilog Hardware Description Language

Overview

• IEEE Std 1364-2005 was a revision of IEEE Std 1364-2001, aiming to correct and clarify features ambiguously described and resolve incompatibilities.
• Verilog HDL is used in all phases of electronic system creation, supporting development, verification, synthesis, testing, communication, maintenance, and procurement.
• Main audience: tool implementors and advanced users.

Contents of the Standard

• Clauses and Annexes: The document is organized into 28 clauses and 9 annexes.
  • Clauses 1-6: Basics of Verilog, conventions, lexical conventions, data types, expressions, and assignments.
  • Clauses 7-11: Gate and switch-level modeling, user-defined primitives, behavioral modeling, and scheduling semantics.
  • Clauses 12-28: Hierarchical structures, design configuration, timing checks, system tasks, PLI, and protected envelopes.
• Annexes include syntax definitions, keyword lists, and additional informative content.

Important Concepts

Conventions

• Shall indicates mandatory requirements.
• May indicates optional features.

Lexical Tokens

• Consist of whitespace, comments, operators, numbers, strings, identifiers, and keywords.

Data Types

• Nets and Variables: Two main groups - net data types (connections) and variable data types (data storage).
• Value Set: 0, 1, x (unknown), z (high-impedance).
• Nets: Various types such as wire, tri, wand, wor, trireg, etc.
  • Trireg can store values and model charge storage nodes.

Expressions

• Combination of operands and operators to produce results.
• Use in procedural and continuous assignments.
• Operator Precedence: Defined to determine the order of operations in expressions.

Assignments

• Two main types: continuous assignments (nets) and procedural assignments (variables).
• Continuous assignments happen automatically whenever the right-hand side changes.
• Variable declaration assignments are a special case in procedural assignments.

Procedural Constructs

Behavioral Modeling

• Procedures: Initial and always constructs are used to define activity flow. Initial executes once, always executes continuously.
• Procedural Assignments: Blocking (sequential execution) and nonblocking (concurrent scheduling).

Timing Control

• Delay Control: Time delay before executing a statement (# operator).
• Event Control: Execution triggered by events (@ operator).
• Intra-Assignment Timing: Delays within assignments.

Conditional and Looping Statements

• Conditional: If-else for executing statements based on conditions.
• Looping: Types include forever, repeat, while, and for loops.

User-Defined Primitives (UDPs)

• Combinational and Sequential: Two types based on static or dynamic behavior.
• State Tables: Define behavior using input and output conditions.
• Sequential UDPs: Use current state and input to determine the next state.

System Tasks and PLI

• System Tasks: Built-in language constructs for simulation tasks like display and file I/O.
• Programming Language Interface (PLI): Allows interaction between Verilog and C language, providing access to Verilog simulation data through routines.

Encryption and Intellectual Property

• Protected Envelopes: Mechanism for securely handling and distributing Verilog source text.

Key Takeaways

• Verilog HDL provides a comprehensive framework for modeling electronic systems at various levels of abstraction.
• The standard supports both detailed gate-level descriptions and high-level abstract behavioral descriptions, facilitating diverse design and verification needs.