Welcome to Basics of Programmable Logic FPGA History of Digital Logic Design Online Training. My name is Carl. In this training, we will explore the history and functionality of programmable logic devices leading up to the modern FPGA.
You may not know it or realize it, but programmable logic is found just about everywhere. From your HDTV at home, to the cell phone towers in your neighborhood, to the ATMs at your bank, digital logic in the form of programmable logic devices is there. doing everything from controlling how a system works like a CPU to behaving like a traffic cop in high-speed switching applications required for networking and communication.
But what exactly is this technology? Where did it come from and how can it be used in so many different applications? This training should help answer these questions as well as how and why programmable logic technology is so desirable to digital logic designers. This training is a basic introduction to programmable logic devices. To understand how FPGA technology works and how it came about, we'll first explore the history of logic design and how it leads to the creation of the first programmable logic devices.
We'll look at the technologies that make up typical programmable logic devices, past and present. And to understand where we are currently with programmable logic devices and design, we have to first look at where we've been. That means it's important and useful to look at the advent of programmable logic design, and the history of the advances that make current FPGA devices possible.
Early digital logic design requires a designer to use multiple chips wired together on a circuit board or breadboard similar to the one shown here. Each chip included one or more logic gates, such as NAND, AND, OR, or inverters, or simple logic structures, such as flip-flops and multiplexers. Many designs in the 60s and 70s were built using the popular Texas Instrument 7400 series of TTL, which was the first of its kind. or transistor-transistor logic devices. When designing with TTL, the goal was often to create the design with as few chips as possible to reduce cost and minimize bore space.
It was also necessary to design with the current device inventory in mind. For example, if you don't have any OR gates available, can you adjust the design to use NAND gates instead, possibly reducing the number of devices requiring overall improving performance? These types of optimizations require a lot of time and effort. require sometimes complicated manipulations of the logic function equations that's needed to be verified to ensure that the changes did not affect the design's basic functionality. Looking at the basic flow of the creation of a logic design, we can see how this was done.
A logic function starts with the creation of a truth table. The truth table lists all the possible inputs to the logic along with what the associated outputs should be with a certain combination of inputs. For n inputs, there are 2 to the n possible input combinations, and they all must be taken into account. From the truth table, we can create a kernel map.
The kernel map organizes the possible outputs into a grid based on the input organized by rows and columns. When a combination of inputs produce an output of 1, it is called a minterm. Minterms are placed in the grid at the appropriate location to match the inputs that produces them as defined in the truth table.
Once all minterms are entered in the kernel map, boxes can be drawn around the minterms to simplify the input combinations required. These boxes make it easy to create simplified logic expressions. Each box on the kernel map encloses one or more minterms. Taking the common inputs for each box, we can create a logic expression for the function as a sum of products.
Each product term corresponds to an AND gate that creates the correct output with the corresponding inputs. For example, the output is always 1 when A and B are both 1, so this term is included in the expression. To implement this function directly in hardware, we would use two input AND gates, a 6-input OR gate, and an output register or flip-flop if we wanted a synchronous output.
A 6-input OR gate is not readily available in TTL, so smaller OR gates will need to be cascaded, increasing delay and component count. To solve this issue, a TTL designer could rewrite the equation to use NAND logic as shown here. This gives the final logic implementation shown here using standard components found in the 7400 series. This implementation uses only two levels of logic to generate the sum of products.
and a register to create a synchronous output. Only two NAND gates and a register are wasted in this implementation. If we look a little closer at this final implementation, we can make a few observations. In general, most logic functions can be simplified down to a sum of products using the methods seen in the example. These functions can be implemented using two combinatorial logic levels, AND gates to create the products terms, and OR gates to sum up the products.
Inverters on the inputs may also be necessary to provide inverted versions of the inputs to create the desired function. To store the outputs or to synchronize the outputs to other outputs, synchronous logic in the formal register is required. If memory or synchronization is not necessary, the output register could be bypassed. With TTL logic devices, these separate components are wired together either on a lab breadboard or with copper trace on a printed circuit board. Thinking about these generalizations for the implementation of logic functions, what if these gates and registers could be combined into a single device?
What if there are fixed connections from the AND gates to the OR gates, the individual product terms, and from the OR gates to the register? Furthermore, what if there was a way to program the connections between the inputs and the AND gates to decide which inputs should be used and where? This type of thinking led to the first programmable array logic or PAL devices.
With the logic gates and output register fixed as generic logic, the selection and use of any of the inputs or their complements with any of the available logic allowed for creation of any logic function. There are three main sections of a PAL, and these three parts were replicated a number of times to form a complete PAL device. The programmable array shown here is where the desired inputs are selected and routed to the desired AND gate.
Connections are made between the lines coming from the inputs and the lines going to the AND gates to form a wired AND operation. We'll look at how these connections are made in a moment. The outputs of the AND gates form the product terms that make up the sum of products function. The product term goes through an OR gate to generate the final function output which is then fed through a register for memory or synchronization. This section of PAL is often called the macro cell.
While not shown in this basic PAL, some PALs include options for feedback into array for more complicated functions or to bypass the output register completely to create asynchronous output. It should be noted that in most current devices, all three of these sections taken collectively make up what is called the macro cell. This is often the case with CPLD devices, as we'll see later.
The advantages of such a device are immediately obvious. With more logic contained in a single device, fewer devices are needed on the circuit board. Fewer devices mean less board real estate required for implementing logic, area that can instead be used for other components. Fewer devices also means a lower overall cost and power savings. It also makes it easier to test and debug logic functions, since the connections are no longer spread out among multiple devices.
any one of which could be wired incorrectly or be damaged. The PAL can also provide design security. With separate 7400 series devices, it's a simple matter of reverse engineering a design by looking at the components that are used and how they are connected. With an entire design contained in a single device, this is no longer possible. PALs also provide great design flexibility, allowing the designer to create many different designs with a single type of device without worrying about the availability.
You have logic. This flexibility can make programmable logic designs more complicated to implement, but an abundance of automated design tools make the process much simpler and less time-consuming. Perhaps one of the PAL's greatest strengths is its ability to support in-system programmability and reprogrammability. This makes it very easy to fix bugs or update a design without replacing board components.
But how does one program and reprogram a PAL? The key to early PAL device programming and even current flash memory technology lies in special transistors used at wire crossings in the programmable array. These special transistors are referred to as floating gate transistors since they contain a second gate that essentially floats between the standard select gate and the rest of the device substrate.
The two most typical seen types of floating gate transistors are the famous floating gate avalanche injection MOS transistor and the FLOTOX, floating gate tunnel oxide transistor. Without any programming, both type of transistors behave like standard n-type transistors. When voltage is applied to the gate, the transistor conducts between the source and the drain, as shown here with indicated input and outputs. Programming changes this behavior.
Both types of transistors are programmed in a similar manner. With a sufficient programming voltage applied between the drain and the gate, electrons get stuck on the on the floating gate, preventing the transistor from conducting even if a standard operating voltage is applied to the select gate. Thus programming a floating gate transistor sets the transistor to always be off, essentially an open switch. An extra selector transistor is required as a Flotox transistor because unprogrammed Flotox transistors can sometimes behave like P-type transistors, conducting when the gate is at ground. The select transistor prevents this from happening.
The main difference between the two types of floating gate transistors lies in how they are programmed and reprogrammed. Famous transistors require high intensity UV light to force the trapped electrons back into the substrate. Devices that use the famous transistors are referred to as erasable programmable ROMs or EPROMs.
Flowtox transistors can be erased by simply reversing the drain gate programming voltage. Since Flotox transistors can be erased using only electricity, they are used to create electrically erasable programmable ROMs or EEPROMs. This makes them perfect for in-system programming and the basis for some of the programmable logic devices that we'll be discussing. Before there were CPLDs, there were simply PLDs. PLDs were very similar to the PAL devices that came before them, but they added some features that made them truly programmable and much more useful.
Shown here is part of what is considered to be the first PLD, the 22V10. The major advances that distinguish this device from simpler PAL devices were the inclusion of fully programmable macrocells and variable product term distribution. Variable product term distribution is a simple idea. Not every sum of products function required the use of every product term generating AND gate.
By varying the number of AND gates, Per OR gate, simpler functions could be efficiently used logic without wasting gates. More complex functions would not have to rely on delay-adding feedback network to implement. However, the major advances found in the 22V10 is the programmable macro cell.
The macro cells in the 22V10 provided a number of programmable options for what to do with the output from the sum of products function. The programmability of a macro cell also provides the ability to feed back into the array or use the output pin as an input. Two programmable control signals control an output select MUX that outputs either the true or inverted output directly from the combinatorial logic, or the true or inverted output from the macro cell register.
If a combinatorial output is selected and the output enable is not active, the output pin becomes an additional input to the array through the input feedback mux. This flexibility in the PLD macro cell made the 22V10 a truly useful device for implementing logic functions. Some of the features found in the 22V10 macro cell still exist in current devices as we'll see. Extending the idea of the PLD further produced the complex PLD or CPLD.
Similar to the creation of PLDs made up of multiple PALs and macrocells, a CPLD is made up of multiple PLD logic blocks connected to I-O pins and to each other through a programmable interconnect fabric. This was the next logical step for increasing the amount of logic in a single device. The logic block and CPLD are often called a logic array block, or labs, because they each contain their own array of logic.
Each lab is like a single PLD. CPLD labs typically contain anywhere between 4 and 20 macrocells. The programmable array found in a lab is pretty much the same as a PAL or PLD array. However, unlike the variable product term distribution found in PLDs, like the 22V10, the macrocells In CPLD labs typically include extra and gate logic that feeds back directly into the array. This extra logic can be used to form extra product terms called expender terms.
The extra product terms generated by the expender logic can be used in the current macro cell to expand the logic function. The expender term can also be shared and used with other macro cells so that a product term only needs to be created once instead of in each and every macro cell that requires it. This produces a more efficient way of minimizing unused logic.
The caveat to using expander term logic is the extra timing delay that is incurred to generate the expander product term. However, the delays for the using expander term logic are known, so they can be taken into account when placing logic and performing timing analysis. Besides labs, other structures are found in CPLDs that are similar to PALs and PLDs, but in more advanced configurations. The interconnect between labs is often called a programmable interconnect array, the PI or the PIA.
The PI is similar to the programmable array found in PALs and PLDs using the same programmable technologies. However, the PI provides all the routing necessary for transferring data between labs and between labs and IOPins. Through the PI, the input or output of any lab can connect to any other lab or to any I.O.
This is key for having... extremely flexible programmable devices. The other enhancement CPLDs made over PLDs is the addition of separate I-O control blocks. In a PLD, I-O pins are connected directly to the logic. In a CPLD, the I-O pins are separated from the main logic of the device by the PI.
The I-O pins have their own control logic to enable a number of features, such as multiple I-O standards and input, output, or bidirectional operation on any pin. instead of forcing some pins to be input only as was the case with 22v10. We'll look at I-O in more detail when we look at FPGA I-O block in the follow-on training.
As programmable logic devices gets larger and more complicated, the programming of the device themselves gets more complicated. To program the floating gate transistor devices we looked at earlier, the PAL or PLD had to be placed in a special automatic programming unit which will apply the correct programming voltages on the correct I-O pins. This basically goes against the idea of having in-system programmability, since the device would need to be removed from circuit board and placed in a programming unit to be reprogrammed or have some special fixture on the board for programming.
To avoid this, CPLDs and FPGAs include programming interfaces that are separate from the design I.O. One popular interface that is now found on essentially all CPLDs and FPGAs is a JTAG interface. A JTAG interface is a simple 4 or 5 wire serial interface that basically forms a long shift register through a single device or can be chained together through multiple devices.
Typically, a JTAG interface on a device is used as part of a device self-test, to ensure the device was manufactured correctly and is working properly. Data is shifted in on the TDI input and shifted out on the TDO output. If the output matches the input, the device passes the test.
If a PLD itself can generate the voltages required for programming, the JTAG interface can control and guide the chip as to where to apply the programming voltage within the device. This makes it easy to reprogram the PLD in the lab or on a board production line. JTAG is an industry standard so any JTAG interface device will work for device self-test.
However, special controllers are often required to talk to a vendor device over the connection for programming. For example, Intel FPGA devices require the use of a programming cable such as the Intel FPGA download cable or the Intel FPGA parallel port 2 download cable. JTAG programming works fine for EEPROM devices since their programming is non-volatile, but as we'll see later, we'll need some more hardware for programming FPGAs outside of the lab. So CPLDs have advantages over their PLD predecessors while maintaining a number of the same features. Perhaps the biggest advantage CPLDs have over PLDs is the amount of logic and routing options available.
The lab logic and programmable inverts are fully programmable, providing a large amount of design flexibility in a single device. The I.O. features and capabilities of CPLDs far outweighs the simple I.O.
on PLDs with many more options and much more control over how the I.O. should work. As with PALs and PLDs, CPLDs provide instant on-operation and board power-up.
They are low cost and require very little board real estate. Their non-volatile EEPROM Programming architecture makes them ideal for testing and debugging using in-system programming without requiring them to be reprogrammed at board power-up. Altera participated in the traditional CPLD market with the MAX line of products up until the mid-2000s when CPLDs were replaced by FPGAs with on-chip non-volatile configuration flash memory such as those found in MAX 2, MAX 5, and MAX 10 devices.
Now that we've talked about the CPLD devices, we can move on to modern FPGA devices. Modern FPGA devices contain much improved architecture compared to CPLDs. They are still lab-based, but the building block is a logic element or adaptive logic module. They also contain many other specialized blocks such as memory blocks, DSP blocks, PLLs, high-speed transceivers, and hardened IP blocks. We will discuss all of the features of the FPGA architecture in the follow-on online training.
Basics of Programmable Logic FPGA Architecture. Please find this free training on the Intel FPGA Training webpage to explore the FPGA capabilities. Here are some additional references. You can find all information pertaining to Altera's programmable logic on the Literature and Technical Documentation webpage.
You may also find the article, The History of Programmable Logic Technology from Altera's System Design Journal, an interesting read. It's a three-part article that talks about the history of programmable logic in the beginning all the way until the current day FPGA usage. This concludes the training. But one last thing.
When you register for this online training, you should have received a link to a short survey where you can provide feedback. We'd greatly appreciate it if you fill out that survey right now. We're constantly updating and improving our training material, and your feedback helps us create the material that you want. Thank you for your feedback. My name is Carl.
I want to thank you for taking the Basics of Programmable Logic History of Digital Logic Design online training. Best of luck with all of your designs.