CPU Components and Buses Overview

Overview

This lecture provides an overview of the main internal components of a CPU (central processing unit) and the buses connecting the CPU to main memory, explaining their functions and interplay.

Main CPU Components

The control unit coordinates activities, directs data flow, decodes instructions, and handles execution and memory requests.
The program counter (PC) holds the address of the next instruction to execute.
The memory address register (MAR) stores memory addresses for data to be fetched from or written to.
The memory data register (MDR) temporarily stores data being transferred to or from main memory.
The current instruction register (CIR) holds the current instruction being executed, comprised of opcode and operand.
The arithmetic logic unit (ALU) performs arithmetic (add, subtract, etc.) and logical (AND, OR, etc.) operations.
General purpose registers (including the accumulator) provide fast temporary storage for data and calculations.

System Buses

The address bus is unidirectional; it carries memory addresses from CPU to main memory.
The data bus is bidirectional; it carries actual data (binary) between CPU and memory.
The control bus is bidirectional; it carries command and control signals (e.g., read/write, interrupts) across components.

Additional CPU Components

The decode unit translates binary instructions into actionable commands for the CPU.
The status register stores flags indicating CPU status, set or checked during operation.
The clock generates regular pulses (measured in hertz) to synchronize CPU operations—the higher the clock speed, the faster the CPU.
The interrupt register detects and manages interrupt signals, pausing current execution to handle events.
Cache is small, fast memory near the CPU that stores frequently used data for quicker access than main memory.

Key Terms & Definitions

Control Unit — Manages and coordinates all CPU activities and data flow.
Program Counter (PC) — Holds the address of the next instruction.
Memory Address Register (MAR) — Stores memory addresses for access operations.
Memory Data Register (MDR) — Temporarily holds data being transferred to/from memory.
Current Instruction Register (CIR) — Contains the instruction being executed.
Arithmetic Logic Unit (ALU) — Executes arithmetic and logical operations on data.
Accumulator — Register for temporarily holding calculation results.
Address Bus — Unidirectional bus carrying memory addresses.
Data Bus — Bidirectional bus carrying actual data.
Control Bus — Bidirectional bus for control signals.
Decode Unit — Logic that interprets binary instructions.
Status Register — Holds status flags for the CPU.
Clock — Synchronizes components by generating timing pulses.
Interrupt Register — Monitors and manages interrupts.
Cache — Fast, small memory near the CPU for frequent data.

Action Items / Next Steps

Review the list of assembly language mnemonics required for the exam.
Watch upcoming videos for more detail on CPU operation and assembly language basics.

Certainly! Here's a storyboard outlining the Fetch-Decode-Execute cycle in a CPU, showing the key steps and components involved:

Storyboard: Fetch-Decode-Execute Cycle

1. Fetch Step

Program Counter (PC) holds the address of the next instruction.
The address in the PC is copied to the Memory Address Register (MAR).
The MAR sends this address to main memory via the Address Bus.
The instruction at that memory address is read from main memory and placed into the Memory Data Register (MDR) via the Data Bus.
The instruction in the MDR is copied to the Current Instruction Register (CIR).
The PC is incremented to point to the next instruction address.

2. Decode Step

The Decode Unit examines the instruction in the CIR.
It separates the instruction into opcode (operation code) and operand (data or address).
The decode unit determines what action the CPU must perform based on the opcode.

3. Execute Step

The CPU performs the operation specified by the instruction.
This may involve:
- The Arithmetic Logic Unit (ALU) performing calculations or logical operations.
- Reading or writing data to/from registers like the Accumulator or general-purpose registers.
- Accessing main memory to read or write data.
Results of the operation are stored back in registers or memory as needed.

4. Repeat

The cycle repeats by fetching the next instruction pointed to by the updated PC.

Visual Summary

Step	Key Registers & Components	Action
Fetch	PC → MAR → Memory → MDR → CIR	Get instruction from memory
Decode	CIR → Decode Unit	Interpret instruction
Execute	ALU, Registers, Memory	Perform operation and store results

If you'd like, I can help you create a more detailed written explanation or diagram based on this storyboard!