Understanding Control Circuit Design

We will see how to design this control circuit. This control circuit can be designed in two ways. Finally, the goal of control circuit is generating the signals, right? So, we can design a circuit which can generate the signals. So, that is hard wide control unit. There is a second one that is micro programmed control unit. We will see that later. Let me focus on the first one, the first model which is hard wide control unit. In the hard wide control unit, we will be designing the circuit for the control unit. We will see that. First of all you tell me what is the purpose of control unit to generate the signals right which will direct the operations. Now question number one how this control unit should take the decisions depends on the some of the input right. So now we will see the inputs for this control unit one is instruction register you agreed correct. So in instruction register we will be taking opcode bits right so that means whether it is add otherwise load that will be decided by the system. opcode that's why we have to examine the opcode bits based on that you know there will be instruction decoder so that decoder is going to take the input which is nothing but opcode and it will understand what kind of instruction it is okay now based on that that instruction decoder will generate some signals okay i1 i2 i3 so on im that signals are useful for your control signal generator okay now let me summarize In instruction register, opcode bits will be processed by this instruction decoder and the decoder understands what kind of instruction it is based on that it will generate some input like i1, i3, i1, i2, i3 so on, iM. Let's say they are all some of the bit patterns. Example if it is add instruction then maybe we generate a pattern like this. So that patterns will be taken as input by your control unit and it will generate the Control signals finally indirectly it is taking the input from instruction register. That is what I said second one step counter So what is this step counter sir? I will tell you so in risk kind of instructions It is a simple model right we follow the five stage model right stage one We do something fetching then after that we know that right decoding then after that arithmetic after that memory after that store So there are five stages correct now based on the stage You know some part of the circuit should work, right? If you are in first stage, then program counter should be incremented, correct? Similarly, memory should be accessed. That's why appropriately signal should be generated. Can I say one thing? Depends on the stage you have to generate the signals. That's why that step counter is going to give us the information about which stage we are now, which stage we are in now. Sir, how this step counter knows about which stage we are? Simple. Generally, if you design your system like this, for every instruction there are 5 fixed stages. 1, 2, 3, 4, 5. If you design your machine such a way that in every stage you are taking exactly 1 clock cycle. Within 1 clock cycle, if you can generate, otherwise if you can do the work of 1 stage, then each stage takes 1 clock. Sir, what if... my stage is very lengthy that means example let's say you are doing arithmetic see what if arithmetic takes lot of time sir simply increase the clock length that's it okay so really you want to plan your work so that every stage takes one clock cycle can you plan it or not is your question yes we can plan it not a problem already i explained you like you know why each one takes only one clock cycle if it takes little bit more than one clock cycle you then increase the clock cycle you are the designer so increase the clock cycle period so that each operation like that means each stage the work of each stage can be carried out in one clock cycle the only thing which you cannot do is that memory access correct memory access sometimes takes three clock cycles four clock cycles correct so assume that at this moment i will discuss that late again don't worry let me assume that let's say every time if you are getting the data in cache 95% of the time you get it. Then within one clock cycle we can access the memory. That's why the fourth stage also can be done in one clock cycle. The only thing is what if the data is not available in cache. Then we have to wait for three or four clock cycles right. That further what should be the solution I will tell you. That we will be dealing don't worry. Now in that way so every instruction is taking five clock cycles. What we do is we use a clock generator. The clock generator should generate you know clock signals. So how to identify you know whenever a clock signal I mean so this clock is generating the timing. So what we do is if you connect this clock to step counter what this step counter should do is whenever it is a first clock cycle in the computer whenever you switch on the computer let us say let us start counting the clocks. Okay, assume that you know this clock is generating the clock like this. Clock 1, clock 2, clock 3, clock 4. Someone should count it. Step counter is going to count it. So, did you know one thing? In our instructions, there is a periodicity. Correct? What is that? In the first clock cycle, fetch, then decode, then after that ALU. Correct? Recall. Fetch, decode, ALU, memory, store. Then again, fetch, decode in that way. So, this step counter is going to generate 5 patterns like this. 0, then 1, then 2, then 3, then 4, then 5. In that way, assume that let us say in digital you learn how to create a counter, correct? Now, assume that let us say this counter is going to oscillate between 0 to 5 like this. 0, 1, 2, 3, 4, 5. Again 0, 1, 2, 3, 4, 5. In that way, if this step counter generates this kind of patterns, then 0 can be used for the first clock. Sorry. 0, 1, 2, 3, 4 then again 0. Then 0 can be used for fetch stage, 1 for decoding, 2 for ALU, 3 for memory in that way. So, we can use it. Now, that means finally sir, how this step counter should generate the numbers like how often I will tell you. For every system clock, it should be incremented. That means you know whenever one clock is done that means you know one clock period is done then it should be incremented such a way we can plan that's why our system clock should be connected to step counter so that for every clock period so this clock will tick based on the tick this step counter should increment its timer value in that way step counter is going to generate 0 1 2 3 4 now this control signal by seeing the binary patterns example assume that let's say we have 5 bit of course it is not required 5 bits Let for simplicity we assume that we have 5 bits and that step counter is generating like this. 0 0 0 0 0, next 0 0 0 0 1, 0 0, you know, that is why 5 bits are not required. If you have 5 bits, we use like this. 0, let us take only 3 bits, okay. 0 0 0, then 0 0 1, 0 1 0, 0 1 1, okay, 1 0 0, 1 0 1. After that again and even 5 also not required right only 4 okay 4 1 0 0 then 0 0 0 again 0 0 1 in that way so if this step counter generates this kind of bits 0 0 0 that will be used as signals and your control signal generator is going to you know understand that by these patterns by seeing these patterns now currently the system is having third clock cycle system is now in the phase of fourth clock cycle in that way so your control signal generator can understand what is the situation is it a fetch stage otherwise decode stage or ALU stage easily your control signal can generator can understand that's why input should come from the step counter okay sir don't worry about the circuit creation now it's not a big deal if you know digital electronics okay at this moment i'm just giving rough idea high level idea so finally we have to take instruction register and we have to understand what kind of instruction and we do that by this I1, I2, I3, so on signals. Now by this step counter, we understand what time it is now. It is a step fetch time, otherwise decode time, otherwise ALU time. Yes, by step counter we can understand. Now one more thing is conditional signals. Already I told you. Whenever you do ALU operation, then some of the condition signals will be generated. Correct? If you take them, example N bit, Z bit, overflow bit, overflow bit V. Correct? Recall. So using these bits, your instruction flow will change that's why these conditional signals should be taken as input and sir is it not complex circuit yes it's a complex circuit because you know computer is not easy designing the computer that's why don't try to by attending this lecture don't try to create you know a computer when you try to create a new computer by just understanding this lecture then definitely you are not doing the right thing we are first understanding the concept slowly you know to really create a computer you need lot of work so these are all high level ideas not exact ideas okay now external inputs also required sometimes example let's say some keyboard is generating a interrupt signal that also should be considered because based on that your flow is going to be changed that's why your final control signal generator should consider instructions Step counter that means which stage you are it will be decided by the step counter that means clock signals and External inputs and conditional signals see this counter enable bit sir Why this counter enable signal for the step counter everything we understood but why this counter enable now, please recall that memory interface Already I told you so even you have a memory interface. This is your memory Okay, and this is interface. Sometimes you can't access the memory in one clock cycle, correct? But what was your assumption? In the first clock cycle, you want to do fetch. In the second clock cycle, you want to do decode. In the third clock cycle, you want to do execution, that means ALU. In the fourth clock cycle, you want to access the memory. So, at fourth clock cycle, when you are accessing the memory, what if that is not done in one clock cycle, then this step counter will go to the fifth clock cycle then control signals will be generated such a way that fifth clock cycle that means you know writing operation will be done right after that again it will go to fetch cycle but everything will be malfunctioned the reason really fourth clock cycles functionality is not done in one clock cycle because of the memory delay that's why what we can do is we can Disable this counter enable that means we can you know make it zero whenever counter enable is zero then step counter will not start will not increment okay. Example let us say I will show with the example so that it will be easy. Step counter generates zero. Whenever step counter generates zero then control signal will be properly you know will be generated so that control signals will be generated so that fetch will be done after that one after that two after that three. After that 4. So whenever this counter enable is 0 at that time, see what we do is whenever there is a memory delay, we struck here, we will stop here and after that we do not increment this counter. So what happens? After 4 we will be in 4 only. After 4 we will be in 4 only. So that these control signals will not change. Everything is same. Since control signals are not changed, then we will be stopping all the signals that means you know i can say so nothing will work that means fifth stage functionality will not be generated by your control signals when that will again re-happen after some time what happens this memory interface is having one bit did you remember that signal mfc right so that means memory memory function is completed whenever memory function is completed this signal will be generated by from memory so immediately Counter will be enabled back. That means now we'll make it 1 so that it will start working. In high level idea I will tell you. Very simple. This counter enable will be enabled only when you really want to increment the counter. That means whenever you want to increment the clock. If you don't want to increment the clock, that means you don't want to do the next operation, then counter enable will become 0. Example like memory delay. Then we will stall. This is called stalling. We stop everything. that means your circuits will not be you know will be completely stopped no signal will be generated so again the next signals will be generated when this counter will is incremented this counter is incremented only when counter enable will become one but counter enable will become one only when this memory says that operation is done so this memory is going to correct i mean respond with a signal called mfc so we can use that mfc signal here and we can enable and disable this step counter that is what the idea understand so this is about finally heart wide control unit circuit functionality and you know everything

There is a second one that is micro programmed control unit. We will see that later. Let me focus on the first one, the first model which is hard wide control unit.

In the hard wide control unit, we will be designing the circuit for the control unit. We will see that. First of all you tell me what is the purpose of control unit to generate the signals right which will direct the operations.

Now question number one how this control unit should take the decisions depends on the some of the input right. So now we will see the inputs for this control unit one is instruction register you agreed correct. So in instruction register we will be taking opcode bits right so that means whether it is add otherwise load that will be decided by the system.

opcode that's why we have to examine the opcode bits based on that you know there will be instruction decoder so that decoder is going to take the input which is nothing but opcode and it will understand what kind of instruction it is okay now based on that that instruction decoder will generate some signals okay i1 i2 i3 so on im that signals are useful for your control signal generator okay now let me summarize In instruction register, opcode bits will be processed by this instruction decoder and the decoder understands what kind of instruction it is based on that it will generate some input like i1, i3, i1, i2, i3 so on, iM. Let's say they are all some of the bit patterns. Example if it is add instruction then maybe we generate a pattern like this. So that patterns will be taken as input by your control unit and it will generate the Control signals finally indirectly it is taking the input from instruction register.

That is what I said second one step counter So what is this step counter sir? I will tell you so in risk kind of instructions It is a simple model right we follow the five stage model right stage one We do something fetching then after that we know that right decoding then after that arithmetic after that memory after that store So there are five stages correct now based on the stage You know some part of the circuit should work, right? If you are in first stage, then program counter should be incremented, correct?

Similarly, memory should be accessed. That's why appropriately signal should be generated. Can I say one thing?

Depends on the stage you have to generate the signals. That's why that step counter is going to give us the information about which stage we are now, which stage we are in now. Sir, how this step counter knows about which stage we are? Simple.

Generally, if you design your system like this, for every instruction there are 5 fixed stages. 1, 2, 3, 4, 5. If you design your machine such a way that in every stage you are taking exactly 1 clock cycle. Within 1 clock cycle, if you can generate, otherwise if you can do the work of 1 stage, then each stage takes 1 clock.

Sir, what if... my stage is very lengthy that means example let's say you are doing arithmetic see what if arithmetic takes lot of time sir simply increase the clock length that's it okay so really you want to plan your work so that every stage takes one clock cycle can you plan it or not is your question yes we can plan it not a problem already i explained you like you know why each one takes only one clock cycle if it takes little bit more than one clock cycle you then increase the clock cycle you are the designer so increase the clock cycle period so that each operation like that means each stage the work of each stage can be carried out in one clock cycle the only thing which you cannot do is that memory access correct memory access sometimes takes three clock cycles four clock cycles correct so assume that at this moment i will discuss that late again don't worry let me assume that let's say every time if you are getting the data in cache 95% of the time you get it. Then within one clock cycle we can access the memory. That's why the fourth stage also can be done in one clock cycle.

The only thing is what if the data is not available in cache. Then we have to wait for three or four clock cycles right. That further what should be the solution I will tell you.

That we will be dealing don't worry. Now in that way so every instruction is taking five clock cycles. What we do is we use a clock generator.

The clock generator should generate you know clock signals. So how to identify you know whenever a clock signal I mean so this clock is generating the timing. So what we do is if you connect this clock to step counter what this step counter should do is whenever it is a first clock cycle in the computer whenever you switch on the computer let us say let us start counting the clocks.

Okay, assume that you know this clock is generating the clock like this. Clock 1, clock 2, clock 3, clock 4. Someone should count it. Step counter is going to count it.

So, did you know one thing? In our instructions, there is a periodicity. Correct?

What is that? In the first clock cycle, fetch, then decode, then after that ALU. Correct?

Recall. Fetch, decode, ALU, memory, store. Then again, fetch, decode in that way. So, this step counter is going to generate 5 patterns like this. 0, then 1, then 2, then 3, then 4, then 5. In that way, assume that let us say in digital you learn how to create a counter, correct?

Now, assume that let us say this counter is going to oscillate between 0 to 5 like this. 0, 1, 2, 3, 4, 5. Again 0, 1, 2, 3, 4, 5. In that way, if this step counter generates this kind of patterns, then 0 can be used for the first clock. Sorry. 0, 1, 2, 3, 4 then again 0. Then 0 can be used for fetch stage, 1 for decoding, 2 for ALU, 3 for memory in that way.

So, we can use it. Now, that means finally sir, how this step counter should generate the numbers like how often I will tell you. For every system clock, it should be incremented. That means you know whenever one clock is done that means you know one clock period is done then it should be incremented such a way we can plan that's why our system clock should be connected to step counter so that for every clock period so this clock will tick based on the tick this step counter should increment its timer value in that way step counter is going to generate 0 1 2 3 4 now this control signal by seeing the binary patterns example assume that let's say we have 5 bit of course it is not required 5 bits Let for simplicity we assume that we have 5 bits and that step counter is generating like this. 0 0 0 0 0, next 0 0 0 0 1, 0 0, you know, that is why 5 bits are not required.

If you have 5 bits, we use like this. 0, let us take only 3 bits, okay. 0 0 0, then 0 0 1, 0 1 0, 0 1 1, okay, 1 0 0, 1 0 1. After that again and even 5 also not required right only 4 okay 4 1 0 0 then 0 0 0 again 0 0 1 in that way so if this step counter generates this kind of bits 0 0 0 that will be used as signals and your control signal generator is going to you know understand that by these patterns by seeing these patterns now currently the system is having third clock cycle system is now in the phase of fourth clock cycle in that way so your control signal generator can understand what is the situation is it a fetch stage otherwise decode stage or ALU stage easily your control signal can generator can understand that's why input should come from the step counter okay sir don't worry about the circuit creation now it's not a big deal if you know digital electronics okay at this moment i'm just giving rough idea high level idea so finally we have to take instruction register and we have to understand what kind of instruction and we do that by this I1, I2, I3, so on signals.

Now by this step counter, we understand what time it is now. It is a step fetch time, otherwise decode time, otherwise ALU time. Yes, by step counter we can understand.

Now one more thing is conditional signals. Already I told you. Whenever you do ALU operation, then some of the condition signals will be generated.

Correct? If you take them, example N bit, Z bit, overflow bit, overflow bit V. Correct? Recall.

So using these bits, your instruction flow will change that's why these conditional signals should be taken as input and sir is it not complex circuit yes it's a complex circuit because you know computer is not easy designing the computer that's why don't try to by attending this lecture don't try to create you know a computer when you try to create a new computer by just understanding this lecture then definitely you are not doing the right thing we are first understanding the concept slowly you know to really create a computer you need lot of work so these are all high level ideas not exact ideas okay now external inputs also required sometimes example let's say some keyboard is generating a interrupt signal that also should be considered because based on that your flow is going to be changed that's why your final control signal generator should consider instructions Step counter that means which stage you are it will be decided by the step counter that means clock signals and External inputs and conditional signals see this counter enable bit sir Why this counter enable signal for the step counter everything we understood but why this counter enable now, please recall that memory interface Already I told you so even you have a memory interface. This is your memory Okay, and this is interface. Sometimes you can't access the memory in one clock cycle, correct? But what was your assumption? In the first clock cycle, you want to do fetch.

In the second clock cycle, you want to do decode. In the third clock cycle, you want to do execution, that means ALU. In the fourth clock cycle, you want to access the memory. So, at fourth clock cycle, when you are accessing the memory, what if that is not done in one clock cycle, then this step counter will go to the fifth clock cycle then control signals will be generated such a way that fifth clock cycle that means you know writing operation will be done right after that again it will go to fetch cycle but everything will be malfunctioned the reason really fourth clock cycles functionality is not done in one clock cycle because of the memory delay that's why what we can do is we can Disable this counter enable that means we can you know make it zero whenever counter enable is zero then step counter will not start will not increment okay.

Example let us say I will show with the example so that it will be easy. Step counter generates zero. Whenever step counter generates zero then control signal will be properly you know will be generated so that control signals will be generated so that fetch will be done after that one after that two after that three.

After that 4. So whenever this counter enable is 0 at that time, see what we do is whenever there is a memory delay, we struck here, we will stop here and after that we do not increment this counter. So what happens? After 4 we will be in 4 only.

After 4 we will be in 4 only. So that these control signals will not change. Everything is same.

Since control signals are not changed, then we will be stopping all the signals that means you know i can say so nothing will work that means fifth stage functionality will not be generated by your control signals when that will again re-happen after some time what happens this memory interface is having one bit did you remember that signal mfc right so that means memory memory function is completed whenever memory function is completed this signal will be generated by from memory so immediately Counter will be enabled back. That means now we'll make it 1 so that it will start working. In high level idea I will tell you.

Very simple. This counter enable will be enabled only when you really want to increment the counter. That means whenever you want to increment the clock.

If you don't want to increment the clock, that means you don't want to do the next operation, then counter enable will become 0. Example like memory delay. Then we will stall. This is called stalling. We stop everything.

that means your circuits will not be you know will be completely stopped no signal will be generated so again the next signals will be generated when this counter will is incremented this counter is incremented only when counter enable will become one but counter enable will become one only when this memory says that operation is done so this memory is going to correct i mean respond with a signal called mfc so we can use that mfc signal here and we can enable and disable this step counter that is what the idea understand so this is about finally heart wide control unit circuit functionality and you know everything

Transcript for:Understanding Control Circuit Design

Transcript for:
Understanding Control Circuit Design