Hey, friends welcome to the YouTube channel ALL ABOUT ELECTRONICS. So in the previous video, we have seen that how to design the logic gates, using the CMOS logic. So similarly, we can also design any complex Boolean function with the help of the CMOS logic. So in this video, we will take few examples, and through the examples, we will see that how we can Implement any complex Boolean function, with the help of the CMOS logic. So in the first example, some logic function is implemented with the help of the CMOS based circuit. So here, we have been asked to find the expression of this logic function. So if you see over here, then this is the PMOS network, and similarly this is the NMOS network. So as you know, the PMOS network pulls up the voltage of the output to the logic 1, while the NMOS network pulls down the voltage of the output to the logic 0. So with the help of the NMOS network, let us identify the Boolean expression of this given circuit. So as I said, this NMOS Network pulls down the voltage of the output node to the logic 0. So here, this Y is equal to 0, or this Y bar is equal to 1, when the C is equal to 1, and either A or B is equal to 1. So we can say that, this Y bar is equal to the C dot A plus B. Or from this we can say that, this Y is equal to the C dot A plus B whole bar. Or the same thing can also be implemented from the PMOS network. So as you know the PMOS network pulls up the voltage of the output node to the logic 1. And as you know, the PMOS transistor will be in the ON condition, when the input to the PMOS transistor is equal to logic 0. So from the PMOS network, this output node will get connected to the Vdd, when the C is equal to 0, or in other words, when this C bar is equal to 1, or this A and B is equal to 0. Or in other words we can say that, that is equal to this A bar dot B bar. And from the above expression using the De-Morgan's law also, we will get the same result. That is equal to C bar plus this A bar dot B bar. So this is the expression which is implemented with this given logic circuit. So from this we can say that, for the given question this A is the correct answer. On the other way around, from the expression if you want to find the circuit, then also we can do that. So suppose if we have been given this expression Y is equal to this A bar B bar plus C bar, then from the expression also we can implement this CMOS logic circuit. So in that case, if you want to implement the NMOS network, then first of all take the complement of the given function. So in that case, this Y Bar will become this A bar B bar plus C bar whole bar. Or that is equal to this A plus B dot C. That means in that case in the NMOS network, both A and B transistors will be connected in the parallel, and to that parallel connection, the C transistor will get connected in the series connection. And if you see the PMOS network, then that will be the dual of this NMOS network. That means in the PMOS network, this A and B transistor will get connected in the series connection, while the C transistor will get connected in the parallel connection. So in this way from the given Boolean function also, we can implement this CMOS logic circuit. But anyway for the given question, this A is the correct answer. So similarly, now let us see the second example. So in this example also, we have been given this CMOS based logic circuit. And we have been asked to find the Boolean expression, which is implemented by this given logic circuit. So if you closely observe, then this is basically a three input NAND gate. And the inputs to this NAND gate are A B and c bar. And in the previous video, we have already discussed these three input NAND gate. So in this circuit, if you just take this NMOS network, then this network will pull down the output to the logic 0, where both A and B inputs are 1, and similarly this c bar is also equal to 1. That means this Y is equal to 0, or this Y bar is equal to 1, when both A and B are 1. And at the same time the C bar is also equal to 1. Or in other words we can say that, this Y is equal to this A dot B dot C bar whole bar. Or from this we can say that, this Y is equal to this A bar plus B bar plus C. That means the expression of the Y is equal to A bar plus B bar plus C. And therefore for the given question, this A is the correct answer. So similarly now let us move to the next example. So in this question instead of the CMOS logic, we have been given this NMOS logic gate, and we have been asked to find the logic function which is implemented by this given circuit. So if you closely observe over here, then here this pull up network consists of the NMOS transistor. That means this single NMOS transistor will act as a pull-up Network. And the logic function is implemented with this pull down Network. So if you see this NMOS network, then the output Y will get connected to the logic 0, when this transistor A is ON, and at the same time either B or C is ON. Or alternatively, when both transistors D and E are ON. So we can say that, this Y is equal to 0, or Y bar is equal to 1, when this A is equal to 1, and any one of the B or C is equal to 1. Alternatively for this Y bar is equal to 1, this D and E both should be equal to 1. That means this Y bar is equal to this A dot B plus C plus D dot E. Or we can say that, this Y is equal to this A dot B plus C plus B dot E whole bar. And therefore for the given question this C is the correct answer. So similarly now let us move to the next example. So in this example also we have been given this NMOS network, but here we have been given that, this input C and D for the given circuit is equal to 0. So here to get the output Y is equal to 0, what should be the value of the A and B inputs. So here we have been given that, both input C and D is equal to 0. So once again if you observe, then this is basically a NMOS logic gate. Where this upper transistor will act as a pull-up Network. And this lower NMOS network will act as a pull down Network. So here both input C and D is equal to 0. So here, to get this output Y is equal to 0, we need a path through which this output node will get connected to the ground. Now for the NMOS transistor as you know, and the input is equal to 0, then it will act as a open circuit. So here since both C and D inputs are 0, so these two transistor will remain in the OFF condition. That means here to get a path from output to the ground node, both this transistor A and B should be in the ON condition. And that will happen whenever, both inputs A and B is equal to 1. Because for the NMOS transistor, when the input is equal to logic 1, then that transistor will act as a short circuit. And through that path, this output node Y will get connected to the ground terminal. That means in this condition, this output Y is equal to 0, whenever both inputs A and B is equal to 1. And therefore for the given question this C is the correct answer. All right! So now let us move to the next example. So in this question, we have been given the CMOS based logic circuit. And here we've been asked to find the logic function, which is implemented by this given circuit. So first of all if you see over here, then this is the PMOS network, and similarly, this is the NMOS network. So if you see over here, then through the NOT gates, this X and Y inputs are connected to the both NMOS, as well as the PMOS network. So to understand which function is implemented with this given circuit, first of all let us simplify the input connections. So here the input to this first PMOS gate is equal to X bar. Similarly the second PMOS gate is connected to the Y input. Similarly over here, the input to this PMOS gate is equal to X, while the input to this lower PMOS gate is equal to Y bar. Similarly on the NMOS side if you see, then the input to this first NMOS gate is equal to X bar. And likewise the input to this lower NMOS gate is equal to Y bar. On the other end, if you see the inputs for this gate number 3 and 4, then they are X and Y. So in short, these are the inputs for the each transistor. And with the help of it, we can easily find the function of this given circuit. So to find that, first let us consider only this NMOS network. So in this NMOS network if you see, then this output f is equal to 0, or this f bar is equal to 1, whenever this X bar and Y Bar both are is equal to 1. That means, we can say that, this f bar is equal to this X bar dot Y bar. Alternatively the output f will be equal to 0, whenever both X and Y inputs are 1. That means we can say that, this f bar is equal to this X bar dot Y Bar, plus X dot Y. Or we can say that this f is equal to this X bar dot Y Bar plus X dot Y whole bar. Now as you know, this X bar dot Y bar plus X dot Y is basically a XNOR function. So if you take the complement of it, then we will get the XOR function. And we can get the same expression even from this PMOS network. So for the PMOS network, this output f will get connected to the VDD, whenever both X bar and Y are 0 at the same time. That means this f is equal to 1, whenever this X bar is equal to 0, or this X is equal to 1, and this Y is equal to 0. Or in other words this Y Bar is equal to 1. Or alternatively whenever this X is equal to 0, and this Y bar is equal to 0. Or here we can write it as, this X bar dot Y. That means from the PMOS network, this f is equal to is X dot Y bar plus X bar dot Y. And that is nothing but the XOR function. So in this way, a logic function, which is implemented by the given circuit is equal to XOR function. So in the same circuit, if we just interchange the inputs for the NMOS in the PMOS network, then we can also implement the XNOR function. So now if you observe, then the inputs for this PMOS network is equal to X and Y as well as the X bar and the Y Bar. On the other end, the inputs for this NMOS network are X and Y Bar as well as the X bar and Y. So, in this condition, now this circuit will work as the XNOR gate. That means in this way just by interchanging the inputs for this NMOS and the PMOS network, we can also implement this XNOR gate. But anyway, here the given circuit implements the XOR function. And therefore for the given question this D is the correct answer. So similarly, now let us move to the next example. So in this question, we have been asked to find the values of the f, Whenever this enable input is equal to 0, and the 1. So first let us consider the case, when this enable input is equal to 0. So whenever this enable input is equal to 0, then the inputs to this NAND gate are 0, and D. And as you know, when any one of the input to the NAND gate is equal to 0, then its output will be equal to 1. That means in this condition, the input to this PMOS transistor will be equal to 1. Similarly now let us see, what will be the input for this NMOS transistor. So whenever this enable input is equal to 0, then through this NOT gate the first input to this NOR gate will be equal to 1. On the other end, the second input to the NOR gate is equal to D. So we know that, when any one of the input to the NOR gate is equal to 1, then its output will be equal to 0. That means in this condition, the input to this NMOS transistor will be equal to 0. Now as you know, whenever the input to the PMOS transistor is equal to 1, then it will act as a open circuit. Or in other words it will remain in the OFF condition. And similarly for the NMOS transistor, whenever the input is equal to logic 0, then it will also remain in the OFF condition. That means whenever the enable input is equal to 0, then both transistor will remain in the OFF condition. And therefore this output f will be in the high impedance mode. That means whenever this enable input is equal to 0, then the output f will be in the high impedance mode. Similarly now let us see the output, whenever the enable input is equal to 1. So whenever this enable input is equal to 1, then the second input to this NAND gate will be equal to 1. While the first input will be equal to D .That means, the input to this NAND gate are D and 1. And in this condition, its output will be equal to D bar. On the other end, since the enable input is equal to 1, so the output of this inverter will be equal to 0. And the second input to this NOR gate will be equal to D. That means if you see the inputs for this NOR gate, then they are 0 and D. And therefore its output will be equal to D bar. So in this condition if you see, then the inputs for this both PMOS and the NMOS transistor is equal to D bar. And therefore this circuit will work as a inverter. And the output will be the complement of the D bar. That is equal to D. That means whenever the enable input is equal to 1, then the output of this circuit will be equal to D. So we can say that whenever this enable input is equal to 0, then the output of the circuit is equal to high impedance mode. And whenever this enable input is equal to 1, then the output of the circuit is equal to D. So basically this circuit will work as the Tri-State Buffer. That means whenever the enable input is equal to 0, then it will remain in the high impedance mode. And whenever this enabled input is equal to 1, then the output will be same as the input. That means for the given question this B is the correct answer. All right! So now let us move to the next example. So in this question, we have been given this circuit. And we have been asked to find the functionality of the given circuit. So as you can see over here, this A and B are the inputs for the given circuit. So first of all let us simplify this circuit, and let us try to find the function which is implemented by the given circuit. So let's say this is the first PMOS transistor. And this is the second PMOS transistor. Similarly this is the first NMOS transistor. And this is the second NMOS transistor. So here the input to this first NMOS transistor is equal to B. And similarly the input to the second NMOS transistor is equal to A. And the same input is also connected to this second PMOS transistor. That means the input to the second PMOS transistor is also equal to A. And similarly the input to this first PMOS transistor is equal to B. So if I just simplify the circuit, then this is how it will look like. So in this condition if you see, then this output F will get connected to the VDD, whenever both PMOS transistor are in the ON condition. Because here both PMOS transistors are connected in the series connection. That means whenever both transistors are ON, then and then only his output F will get connected to the VDD. And for that to happen both inputs A and B should be equal to 0. So we can say that this output F is equal to 1, whenever both inputs A and B are 0. On the other end, let us see what happens when A is 0 and B is equal to 1. So whenever this A is equal to 0 and B is equal to 1, then first of all this PMOS network will remain in the OFF condition. Because this transistor B will remain in the OFF condition. On the other end, if you see this NMOS network, then here this A is 0 and B is equal to 1. So here since A is equal to 0, so this NMOS transistor will also remain in the OFF condition. On the other end, this transistor will get turned ON, and its output will get connected to the F. That means in this condition, if we see and the F will be equal to 0. Or in other words, we can say that, whenever this A is 0 and B is 1, then this output F is equal to 0. And the same thing will also happen, whenever this A is 1 and B is equal to 0. So in that condition, also this output F will be equal to 0. So in this third condition, this transistor will remain in the ON condition, while this transistor will get turned OFF. And since the B is equal to 0. So this F will get connected to the 0. That means in these two conditions, this output F is equal to 0. So now let us see the last condition, when both A and B is equal to 1. So whenever both A and B is equal to 1, then once again this PMOS network will get turned OFF. Because in this condition, both the PMOS transistors will remain in the OFF condition. On the other end, since both A and B is equal to 1, so both the NMOS transistors will remain in the ON condition. And they will get connected to this A and B node. So since A and B both are 1, so this output F will also be equal to 1. That means in this condition, this output F is equal to 1. So if I just summarize, then this output F is equal to 1, whenever both A and B is equal to 1. And the second case is when both A and B is equal to 0. So we can say that, this F is equal to this A dot B plus A bar dot B bar. So this is the logical expression for the given circuit. And as you know, this function is nothing but the XNOR function. So we can say that the function, which is implemented by the given circuit is nothing but the XNOR function. So I hope through these examples, you understood how to implement any complex logic function with the help of the CMOS logic. So if you have any questions or suggestion, then do let me know here in the comment section below. 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