Lecture Notes: Switch Level Modeling Using Verilog

Introduction

• Topic: Switch level modeling using Verilog
• Objective: Understand how to model circuits at the transistor and switch level, not just gate and functional blocks.

MOS Transistors

• Types: nMOS and pMOS (based on impurities in source and drain regions)
• Use Case: Typically, designers do not model using transistors but may use them for low-level modules (leaf-level) in hierarchical designs.
• Example: Implementing an XOR gate using MOS transistors and using it in higher-level designs.

Switch-Level Modeling

• Concept: Model transistors as switches.
• Transistor Representation: (Diagrams not included)
  • nMOS: Gate, Source, Drain
  • pMOS: Similar to nMOS, with differences in control signals

Verilog Facilities for MOS Level

• Logic Values: 0, 1, x, z
• Signal Drive Strength: Importance in modeling
• Switch Types: Ideal and resistive
  • Ideal Switch: Zero resistance when closed
  • Resistive Switch: Low resistance, not zero; causes signal strength to decrease

Switch Level Primitives in Verilog

Ideal MOS Switches

• Keywords: nmos, pmos, cmos
• Resistive MOS Switches: nmosr, pmosr, cmosr
• Bi-Directional Switches: tran, tranif0, tranif1
• Resistive Bi-Directional Switches: r + respective keywords
• Power Supply Keywords: supply1 (Vdd), supply0 (GROUND)
• Pull-up/Pull-down Keywords: pullup, pulldown

Instantiation of Switches

• nMOS & pMOS: nmos (instance_name, output, input, control);, pmos (instance_name, output, input, control);
• cMOS: Includes complementary nMOS and pMOS, declared with cmos (instance_name, output, input, n_control, p_control);

Examples of Verilog Models

CMOS Inverter

• Diagram: (nMOS and pMOS in series)
• Verilog Code Example: (Description and Implementation)

module cmos_not(input x, output f);
  supply1 vdd;
  supply0 gnd;
  pmos p1(f, vdd, x);
  nmos n1(f, gnd, x);
endmodule

Two-Input NAND Gate

• Explanation: Two nMOS in series, two pMOS in parallel
• Verilog Code Example: (Description and Implementation)

module cmos_nand(input x, input y, output f);
  supply1 vdd;
  supply0 gnd;
  wire a;
  pmos p1(f, vdd, x);
  pmos p2(f, vdd, y);
  nmos n1(f, a, x);
  nmos n2(a, gnd, y);
endmodule

Pseudo nMOS NOR Gate

• Explanation: Pull-up resistor configuration, two nMOS transistors
• Verilog Code Example: (Description and Implementation)

module pseudo_nor(input x, input y, output f);
  supply0 gnd;
  nmos n1(f, gnd, x);
  nmos n2(f, gnd, y);
  pullup(f);
endmodule

Two-to-One Multiplexer

• Explanation: Uses two cMOS switches controlled by select inputs
• Verilog Code Example: (Description and Implementation)

module mux2to1(input s, input i0, input i1, output out);
  wire sbar;
  not n1(sbar, s);
  cmos c1(out, i0, sbar, s);
  cmos c2(out, i1, s, sbar);
endmodule

Bidirectional Switches

Types

• tran: Always conducts
• tranif0: Conducts if control signal is 0
• tranif1: Conducts if control signal is 1

Conclusion

• Usage: MOS switch primitives are mainly for simulation, not supported in synthesis tools.
• Next Lecture: More examples on switch level modeling and additional discussions