Transcript for:
Switch Level Modeling Using Verilog

[Music] so in this lecture we shall be moving away slightly from what we have been discussing and we shall be looking at something called switch level modeling using verilog now this is something which we thought that as a designer someone should know that how we can model some circuits not only at the level of gates and functional blocks but also at a lower level when our building blocks are transistors and switches ok so we shall see what are the facilities that are provided by the language verilog and what kind of modelling you can do or carry out using that ok lets see so so when you talk about switch level circuit basically we are talking about a circuit that consists of mos transistors now for those of you who are familiar with mos transistors i mean will be knowing that there are two kinds of mos transistors those are the nmos and pmos depending on the kind of impurities you put in the source and the drain regions right ok now the point to notice that as a designer when you are using verilog to design a digital circuit it is not very common for you to design a model using transistors but there may be some very specific cases where a low level model which is sometimes called a leaf level module you can be using mos transistors to model them as a hierarchical design just i am giving an example suppose you want that well verilog provides gate level primitives and or nand nor xor all right but you want some your own design using mos transistors to implement some gate so you can write a very low level module using mos transistor let us say to implement an exclusive or gate and that xor gate you can use you can instantiate it in higher level designs to create more complex designs so it is only under these conditions you can possibly use switch level modeling ok normally you do not use switch level models in a real design now as i said verilog provides some facilities for modeling at the mos level where the transistors are regarded as a switch you see in mos level a transistor is represented like this this is called the gate and the other two terminals one of them is source other is drain this is an example of an nmos transistor the symbol and pmos transistor is same where there is a bubble here same kind now we are regarding a transistor as a switch let's see what is the switch a switch schematically represent like this there are two terminals x and y they may be connected if i close this switch they will be not be connected if i open this switch here also depending on what voltage i am applying to gate either this source and drain may be conducting they may be connected or they may not be connected so you can regard a transistor as a switch that is what is meant by switch level modeling right so earlier we have seen that in verilog there are 4 logic values which are supported 0 1 x and z and earlier we also talked about signal drive strength drive strengths now here when you are just working with mos transistors and the basic primitives we shall be seeing we shall be appreciating that why the signal drive strengths are required in the modeling and regarding the switches there are two types of switches which are supported one is called ideal other is called resistive now an ideal switch means when you close a switch there will be zero resistance and a resistive switch means when you close a switch there will be a low resistance but not zero a finite low value of resistance so if there is a low resistance what will happen is that if we apply a signal at one side on the other side the strength of the signal will be reducing a little bit this is how the concept of signal strength comes in ok when a signal is passing through a resistive switch the strength of the signal decreases ok fine now the various switch level primitives which are supported by verilog are as follows the first are the ideal mos switches they are represented by these primitives n mos p mos and c mos we shall see them there are resistive versions of these also just an r before these names very similar but there will be a non zero resistance here and these switches are normally assumed to be conducting current in one direction but there is another kind of a switch which is called bidirectional switch which is assumed to conduct in both directions ok so you can have bidirectional switches also these are denoted by tran tran tran if zero tran if one will see what these are and similarly there are resistive versions of these switches with r and blue and there are some keywords to indicate supply voltages power supply one and supply zero directly you can mention them and there is something called pull up and pull down this also we shall see now let us come to nmos and pmos switches first this nmos and pmos switches they are declared with the chemo keywords in mos and pmos now as i shown you earlier this is a schematic of an nmos transistor acting as a switch and this is a pmos transistor there are two input and output terminals and there is a control gate is the control here also is similar now the way it works is that if the control for an nmos switch if the control is at high if the control is one then the gate is conducting so if the input is zero this is input then the output is zero this is output if the input is one the output is one but if the control is zero then the switch is off so the output will be in the high impedance state it is not connected to anything ok just ignore these two columns for the time being if the control is either undefined or in the high impedance state well the verilog language specifies that if we apply a 0 the output voltage will also be at the low level ground level if we apply a 1 the output will be at a high level because there is no voltage drop but if you apply i means x and z in the input then the output will be indeterminate x and z similarly for a pmos it is just the reverse if the control is set to 0 then the switch is conducting if the control is one then the switch is off ok we need only this much this this part of the table and the way you can instantiate is you write either nmos or pmos well instance name is optional you can give a name and first the output then the input then the control this is the order this switches are sometimes also called pass transistors well there is a cmos version of cmos stands for complementary mos complementary mass so in a cmos switch there is an nmos switch and a pmos switch which are connected in parallel and there are two control signals n control and p control so when you instantiate it it is output input n control and p control normally this n control and p control are complements of each other say if i apply 1 here and 0 here then it will be conducting if i apply 0 here and 1 here both of them are off so it will be off this is a better switch as compared to a single transistor switch because when you use single n type or p-type transistor the switch there is a voltage degradation which happens but if you use two back to back switches that voltage degradation is avoided so i am not going into the details of this here but just remember this that the cmos switch is a better kind of a switch lets take some example designs a cmos inverter for those of you who have studied mos level gates will just identify this circuit there is an nmos transistor there is a pmos transistor whose gates are connected this is the input and the sources or the drain whatever you call this is the output the other side is connected to power supply vdd and ground this is the symbolic notation now the way it works is very simple if the input x is zero if it is zero then the p type switch is on if it is and the n type switch is off if p type is on then vdd will be connected to the output output will be one if it is zero output is one and if the input is one then the n type will be conducting this switch is on so the output will be connected to ground output will be zero so it is not gate so you can directly specify this net list in verilog like this let us call it cmos naught x is the input f is the output so input x output f so here you are using vdd and ground terminals also thats why you define two variables one you call as vdd another called gnd of type supply one and supply zero there is one pmos transistor let us call it p1 f and vdd are the two terminals this is f and this is vdd and the gate is x similarly there is another transistor nmos let us call it n one f and ground are the two terminals and the input is x so this is the complete description similarly you can have a nand gate two input nand gate so two input nand gate there are two n type transistors here and two p type transistors here for a nand gate you recall when both the inputs are one one output is zero so when both x and y are one and one both the switches n one and n two will be conducting on so the output will be connected to ground it will be zero but if if any one of them is zero so either p one or p two will be conducting so there will be a a path from v d d to the output so the output will be one so if any one of the input is zero output is one that is nand so description see you see means i am not here trying to teach you how to design circuits using mos transistor so what i am saying is that given a mos level circuit how to model it in verilog you see this circuit can be model in verilog like this x y and f inputs are x y output of again vdd ground are the two supplies and intermediate there is one line a i declare it as a wire pmos just this p one f v d d x f is this this is f this is v d d and this is x for p two f v d d y f v d d y now for n one they said f a x f a x and for n two ground a or a ground whatever order you specify and y a ground y ok now this nmos nand if you write a simple test bench to see whether it works or not so so you can simulate and see that it works really works so we have instantiated this cmos nand in a test bench like this we called it my nand two in one into out the inputs you declare as reg out as where and defined an integer k so why just in order to apply all possible inputs you see this is a two input circuit so what we did in this initial block we gave a for loop which runs from k equal to zero up to three k less than four zero one two three there are two inputs so the combinations will be zero zero zero one one zero and one one which means zero one two three i am counting in decimal ok that k so in k i am counting decimal zero up to three and that value of k i am assigning to the inputs using concatenation operation say for example if case three it means one one in one will be one into will be one so this will be happening automatically and we are displaying the values of n one into an out so if we just simulate it we get this result zero zero output is one zero one output is one one zero one one one zero this is an end ok fine let us take another example this is called pseudo nmos nor gate ok but before we explain this let us tell you about the primitive that are available pull up and pull down see you can ah with a signal let us say x you can either write pull up x or with a signal y say x you can write pull down x what does this mean pull up x means there is a signal line x pull up means from here you are connecting a resistance to supply 1 that means positive supply voltage this is called pull up so when you say pull up this whole thing will be included by default there so the meaning of pull up is that suppose this output you are feeding to the input of some gate let us see and because of some reason this x is in the high impedance state let us say x equal to z then because of the pull up this input will still be at one because it is connected to the supply with the resistance so it will not be in the high impedance the input will not be z similarly pull down means this x is the signal you connect a resistance to ground this means pull down so in circuits we often use this kind of pull up and pull down configurations to implement several things like here we are showing an alternate way of dif of designing gates this is this a nor gate and this is called pseudo nmos pseudo means here you have a resistance in the pull up and down you have two nmos transistors you see why it is not in a not gate how does it work so if the inputs are zero zero then only the output is one otherwise the output is zero ok let us say here if the inputs are zero and zero both the transistors are off so f is not connected to ground so f will be connected through this pull up to one so f will be high out one but if any one of them is zero that transistor will be on and f will be connected to ground now c f is connected on one hand to the ground through an on switch on the other side it is connected to a pull up resistance to a supply voltage so will the output be ground or high you see the the idea is pull up or pull down has a lower signal strength because of the resistance so when two such signals are tied together the signal which is stronger it will dominate like here on one side you are trying to connect to ground on the other side you are connecting to one but ground is a stronger signal here so ground will dominate because this is ideally zero resistance so f will be zero right okay so declaration is very simple x y input f is the output and here we need to declare only ground supplies g and d there is one n mos n x another n mos n y f ground x f ground x f ground y and there is a pull up at point f at point f there is a pull up this is the model description so this module in a same way if you do a simulation that same test bench we have just included minor instead of the other one pseudonor so if you simulate it remaining part is same you see the output is coming like this zero zero is one otherwise output is zero this is not so this one more example let us take here we use a cmos switch just see this diagram there are two cmos switches one cmos which is here another cmos switch is here and there is a we are implementing a two to one multiplexer and the two inputs are connected to the cmos switches and the select line s is connected to the nmos transistor of one of the switches and to the pmos transistor of the other switch ok and there is a not gate not of s is connected to the p transistor of this switch and n transistor of this switch what does this mean if s is 0 if s is 0 then this will be 1 not this will be on this will also be on so this switch is on but this switch is off because this is on i 0 will go to the output and if s equal to 1 then this will be on and also this will be on but this will be off so i 1 will go to out so representing verilog is very simple this input s i 0 i 1 output is out and there is an intermediate line output of this not gate i call it s bar so i instantiate this not s is the input s bar is the output and two cmos gates i have just instantiated one i call cmos a otherwise called cmos b so the inputs are how output the i zero and control is i means s bar in ah means n type and s in p type so s bar n type and p type and for cmos b out this is i one and here it is s in p tie i mean s in n type and s bar in p type s and s bar so this again see here there are three inputs total right so we have written a test bench similarly but we have applied eight pattern zero up to seven and this k is assigned to select in zero in one like this so we have printed the values of cell in one this should be in zero actually in zero in one and out so you see if select is 0 then in 0 is getting selected if select is 1 then in 1 is selected 0 1 0 1 is getting selected right so it works as a multiplexer so and lastly in this lecture we shall be talking about something called bidirectional switches of course we will not be giving example just to tell you what it is see in a normal switch pmos nmos or cmos well it is assumed that current flows in only one direction but this is only for the purpose of simulation in a real switch current actually flows in both directions so if in a design you need to have a switch where you need current to flow in both directions then you should use something called bi-directional switches which are called trun so there are three kinds of bi-directions which is tran tran if zero and tran if one so the syntax of the trans which is tran well instance name as usual is optional means because it is bi direction i call them in out in out one in out two the two terminals and this is always conducting but tran if zero and run if one means there is a control signal tran if zero says if the control signal is zero then it will conduct and tran if one says if the control signal is one if one then it will conduct and if it is control is other way round then output will be tri-stated this will be off ok this is how the bi-directional switches work so with this we come to the end of this lecture where we talked about some of the low level mos switch primitives which also you can use in verilog modeling but again i am telling you these are mostly used for simulation purposes most of the synthesis tools will not be supporting this kind of mos level primitives so in the next lecture we shall be looking some more examples on this kind of switch level modelings and a few other things thank you