Notes on Gabrielle Manganaro's Talk on High-Speed ADCs

Speaker Introduction

• Gabrielle Manganaro
  • Doctor engineer in 1994, PhD in 1997 in electronics from the University of Catania, Italy.
  • Worked with Texas Instruments, National Semiconductor, Analog Devices.
  • Director of Technology at Mediatech since 2001.
  • Co-authored over 65 papers, 3 books (notably Advanced Data Converters by Cambridge University Press, 2011).
  • Holder of 19 US patents.
  • Fellow of IEEE (2016) and IET (2009).
  • President for Publications for the IEEE Signal Processing Society (2023-2024).

Presentation Overview

• Main Focus: Discussing non-ideality limitations in high-speed ADCs, rather than improving ADCs themselves.
• Key Non-Idealities Addressed:
  1. Input Bandwidth Limitations
  2. Sampling Clock Jitter

Key Points

1. Input Bandwidth Limitations

• Strays from PCB, packaging, and ADC contribute to bandwidth limitations:
  • High-speed ADCs can perform poorly due to these strays.
• Sample Rate vs. Input Bandwidth:
  • Example: ADCs sampling at 10 GHz may only have effective input bandwidth of 6-8 GHz.
  • Need to solve this issue to exploit high sample rates effectively.

2. Sampling Clock Jitter

• Impact of Jitter on Sampling:
  • Clock jitter introduces noise and affects the sampling time.
  • Results in errors in the digital representation of the signal.
• Statistical Distribution of Jitter:
  • Jitter RMS value directly impacts SNR.
  • Example: Acceptable jitter for 10-bit ADC at 1 GHz is around 160 fs RMS.
• Frequency Domain Impact:
  • Phase noise increases jitter effects, causing large noise skirts.

Solutions Proposed

Input Bandwidth Extension

• Bandwidth Extension and Signal Conditioning:
  • Need to filter and adjust signal amplitudes before supply to the ADC.
  • Proposed architecture includes:
    • Variable gain amplifier
    • Fixed gain amplifier
    • Attenuator to maintain bandwidth while adjusting gain.
    • LC filtering integrated to avoid bandwidth degradation.
• Results:
  • Achieved input bandwidth extension up to 30 GHz.

Continuous Time Pipelining to Mitigate Clock Jitter

• Continuous Time ADC Structure:
  • Moves the sample hold function within the ADC to mitigate jitter effects.
  • Uses sub-ADCs for MSBs and further stages for LSBs.
• Jitter Mitigation Techniques:
  • Interleaved sampling clocks increase effective sampling frequency, reducing jitter impact.
  • Results in 3 dB better digital tolerance to clock jitter.

Challenges and Considerations

• Power Consumption: High-performance ADCs often require significant power, especially for clock generation.
• Radiation Tolerance: Discussed but indicated that the design was not intended for radiation-hard applications.
• Further Research Directions: Improvements in low-power biasing for ultra-low power circuits were hinted at as an area of interest.

Conclusion

• Summary of Achievements:
  • Presented a methodology for overcoming limitations in high-speed ADCs.
  • Demonstrated effective techniques to enhance performance while managing power consumption.

Audience Questions

• Addressed various inquiries from the audience regarding applications and future improvements in the ADC design.
  • Included discussions on practical applications stemming from Manganaro's research and insights on future trends in the field.

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Note for Review:

• Be sure to study Manganaro's papers for deeper insights into his research and contributions!