but today we are here to attend the talk by Gabrielle manganaro so talking about improving limitations of highspeed adcs so Gabrielle manganaro received a doctor engineer in 94 and PhD 97 degrees in electronics from the University of katania in Italy he was with Texas Instruments National semiconductor and analog device uh since 20 1 he works at mediatech as a director of Technology he coauthor over 65 papers three books notable Advanced Data converters by Cambridge University press in 2011 and has been granted 19 USA patents so a very nice number of patents and he is a 9o fellow since 2016 a fellow of the IET since in 2009 and this presently serving as president for Publications for the I secing system societ for 2023 24 so thank you very much Gabrielle for accepting our invitation and the floor is with you to start your presentation thank you so much for your invitation it's a it's a honor to be here and uh uh so I'll uh I'll get started uh so to begin with I'll um U summarize what I'm about to describe uh this presentation it's actually not about making better adcas but it's about overcoming or mitigating a number of non- idealities that impact uh the uh performance of I speed adcs and their ability to use them and uh I'm going to be um uh dealing with two major non idealities which affect the two of the input of any highs speeed ads the actual signal input and the uh input where we provide the sampling clock so uh regarding the signal input uh the issue that I'm going to be uh dealing with is essentially that because of the uh contribution of multiple Strays that arise from the PCP the package and the ADC itself uh the input bandwidth of the ad C can be severely limited and uh and therefore even a very high sample rate ADC can can suffer of that and the second uh limitation has to do with the sampling clock Jitter which uh it is well known to be a fundamental limitation uh if you have a jic clock that will make uh the ability to capture the input uh problematic because uh the sampling time time will be uh much less determined and uh we will see that uh uh there are ways to mitigate this problem when we consider uh continuous time pipeline to this so This slide um shows an ideal uh sampling uh signal chain where we have a s a an input a signal source which for example in the frequency domain may be May consisting into two separate communication channels and they are within the first Nyquist uh band So Below FS over two where FS is the sample rate and then this uh uh ideal Source um it's applied to an NL as in filter uh which purpose as you know is to limit the uh the input frequency content to to first n and and filter out beyond that in order to avoid aliasing of of noise or other or other signals back into band so this is the transfer function of the anism filter and ideally the output of the anism filter gets on chip this is this line is meant to to show the boundary or what's on chip from what is of Chip so the input gets sampled by a sample and hold the sample and hold is triggered by a clock that is at a frequency fs and so uh ideally in this situation uh the the input it's band limited by the nlsm filter gets sampled and after conversion we get uh we get our digital representation of the input so this is all nice and well uh however as we consider real um uh real effects uh due to PCB to packaging etc etc we will see that uh there are some limitations that need to be addressed so for example in this diagram we see a more complete um lineup where in addition to what I just described now we have uh we are modeling the presence of Strays which I'm here simplifying in a in a cartoonish way with a simple low pass filter there with a with an inductor and a capacitor and uh here I'm representing again in a simplified way the presence of the ESD protection circuit which is required at the on the input of the die in order to avoid the damage from electrostatic discharge and so the problem with that is that block like this effectively will introduce an additional uh low pass filter in to the to the input between goes into the chip uh and finally actually makes it to the sample and hold uh we should also uh definitely remark that the sample and hold itself which is typically a switch capacitor circuit will also additionally band limit the input because the the the cap the sampling capacitor itself will have a likely a value that it's not insignificant so when you combine all of this um you may end up actually with the pass band uh at the at the input of the sample and hold that may be uh inferior to the uh to the Nyquist sample rate so to give you a sense of the severity of the problem if uh there are many state-ofthe-art ieed converters that are uh beginning to sample uh at 10 of of gigahertz and uh it is not at all unusual that when you consider uh the the the the effect of all these trays you may end up with the input bandwidth of the order of six to 8 gahz so so what is the point of having uh a Nat samples at 20 or higher uh gigz if you can't get the input really you know beyond six or seven GHz so we have a problem that needs to be solved um so in addition to this uh we also have to deal with the well-known problem of the sampling clock Jitter and uh as you will know from textbooks the issue here is that uh if we uh control the sampling switch of a sample and old or a track and hold with a jittery clock what happens is that the actual time of sampling which is determined by the time when the clock turns off it's uh it's going to be noisy it's going to be affected by phase noise which will translate depending on the slope of your input signal will translate into into an error uh over the input signal and so once you sample with a jic clock uh this error especially if the juder is essentially noise likee it's effective face noise like it's going to result into a a limitation on the best SNR you could possibly get by sampling this signal and this is a well-known formula so as you can see it depends very much for the from the input frequency not the clock frequency and of course it depends on the um statistical distribution of of your uh Jitter so that's the RMS value of the of the Jitter of the clock in addition to this another way to look at this problem is that uh uh not only there will be a statistical uh description of the of the sampling clock but uh if we take um if we take a frequency domain look at the clock itself uh ideally this would be uh a welldefined uh uh you know uh Spike at FS but in fact because of the Jitter you actually are subject to phas noise so the phase is really is really uh again affected by by by noise and the problem is that once you use this clock to sample for example an input which again uh the example here of two communication channels what happens is that the uh the resulting sample um input to the ADC is affected by noise skirts which are nothing else than essentially up converting this noise uh uh through the through the channels so of course if the if the phase noise is excessive this results into large um noise skirts which can result like in this example into desensitizing a weak Channel when this is adjacent to a very strong Channel so again this is a fundamental issue and it happens at the sampling at the sampler and so uh so we need to we need to address this problem so I need to give credit to two of my Coors the material that I'm going to be presenting next it's uh elaborated in great detail in these two papers one published at the blsi conference two years ago and another one uh the the the year after but it's there is a journal version um appearing within days on the journal solid state circuits um so let's talk about the first problem the input bandwidth uh limitation and so we will deal with bandwidth extension and Signal conditioning because in addition to the problem that I just described the input band with being too narrow and needing an extension we also need to account that it is very desirable in modern application such as if we went want to do um direct RF digitization or some of of signals well into the millimeter wave or for instrumentation application it's very important not only to extend the bandwidth in order to be able to capture the signals but in addition we need to be able to adjust the signal to be able to amplify it or attenuate it so that the input signal can be made to fit as much as possible to the input range of the ADC so but simply we need to essentially add a gain adjust or a tenor we also need to filter the input uh in order uh not to be able to in order not to be subject to uh unintended signals that are out of band whether these are blockers or it's or it's noise and uh so uh and we need to of course do all the signal conditioning without without uh deteriorating the input too much in other words without adding excessive Distortion and an additional noise to the input before we actually can supply that to the a2d now state-ofthe-art in most cases most Publications is that uh some of these functions are are dealt with unity game buffers there is very little at all in terms of amplification Etc and we're talking about um uh order of several gahz we're going to try to show that this can be done well into the uh nearly 30 gz range uh so this is the proposed uh demonstration of of what we have done we uh did a test chip and I'm going to describe the different functions so to to begin with the first block consist into uh a variable uh attenuator so let me start back one minute we can do a again adjust by having uh a variable gain amplifier however the problem with that especially this frequency is that as you adjust the gain uh you have you will be subject to changes of course in band with in noise Etc so a different way to accomplish this is to actually have a fixed gain which is this block over here and then of course buffer it before it goes to the sample and hold and then in front of that actually add a variable attenuator which will keep as much as possible the overall bandwidth constant while being able to essentially adjust the com the complete gain the combination of this attenuator with the fixed gain amplifier so uh in an addition to this over here we will also do LC filtering uh and we will want this LC filtering also not to change bandwidth or behavior as we move the game uh so after that we have a a fixed gain amplifier with constant bandwidth and constant Distortion and noise and then finally for the purpose of evaluating this test chip we added of course some um some termination and uh and protection and this uh chip was uh actually tested using uh wafer probing and so on anyway so going to the implementation this diagram shows you the variable uh attenuator which has actually been combined together with the uh input filter we also want to have a filtering uh that uh in this case uh uh shows a a cherf response and uh the different blocks that we use to to control the attenuation uh actually are part of the filtering and the other point that I want to make here one of the limiting elements is also the ESD protection uh which in which introduces straight capacitance and what we did is that we essentially broke the protection circuit in two two blocks uh uh esd1 and esd2 which combined together provide the same level of protection however by doing so and by intro and by making them ESS part of this filter we were able to uh uh to mitigate the effect of their large capacitance are now spreading it spreading it over and using it as part of the of the filter itself so that's essentially what is shown in this slide now the different blocks of the attenuators basically are individual um uh weighted attenuators as you can see we can attenuate one theb here 2 db4 and four and they are implemented respectively with a pi Network and a t Network and the way this works is that when the network is on so when this switch is off uh you you obtain the the desired attenuation and then when you actually want to uh have a higher gain what you do is turn you turn on the switch this shorts the network and so the signal simply passes through and uh in this case it's the same thing it's just done with a t Cel uh follow the attenuator and the filter uh we have the our uh amplifying stage typically people will use either a common gate or a source follower stage we're we're introducing here a hybrid uh configuration there is a first part which is a essentially a common gate stage so as you can see there is a termination resistor which is well defined and is very desirable especially at this high frequency the signal goes through the termination resistor and then uh goes into the common gate stage here which is complementary and so essentially the amplification consisting to the current here uh flowing through the Rd and that's how you get uh as you can see from the formula here that's effectively how you get the game okay but if you noticed for this uh stage and this is this is a differential as you can see uh we need to of course Supply a biasing current so the question is why not getting more gain out of this by playing a little bit with this uh with this uh bias Cent so what are we going to do well we're going to replace that with a with a a uh common source uh stage which uh uh uh gets the same signal now this time the signal is uh provided here to the Gates of the common uh the common source stages the output of the common source stage it's added together with the one of the common gate and that's how you basically take advantage of the presence of the uh the additional transistors and so effectively now the gain is basically doubled uh Without Really uh Without Really adding a whole lot more Strays and so being able to to provide a very wide band response and to finish up the job we also uh introduce serious sham picking through these inductors which will help essentially extend a little bit the band a little more than than without it this stage then drives an output buffer because now we need to be able to drive the large capacitance of the uh SLE and hold that follows this so that's done with this structure that you can see here it's essentially a pushpull topology which uses a common source amplifier with a two level put strap cast coding now the input signal the differential input signal it's sent to the common source uh amplifier so the the essentially the sorry the The Source follower it's Al also Sim simultaneously sent to the bo strap cast codes so so that gives a um a res in high linearity and of course a best use of the devices etc etc and as you can see here is the difference the D the dash line shows the response uh with estd and and other and other limiting factors but then after all the modifications that I have they have described we can actually extend the bandwidth and and really be able to to to get up to 30 remember we started with something that was of the order of six and now we expanded it to 30 gahz and uh with with very good linearity and noise this is a a photo of the test chip as I said the um the this was evaluated during um wafer testing uh it's implemented in 16 nanometers and uh and uh you can see over here the input filter with of course the digital step attenuator the amplifier the buffer etc etc uh some results uh as you can see here the frequency respones that we intended to obtain uh as you can see the frequency response shape is the same and we are able to adjust linearly the gain uh uh by by working on the uh attenuator so without any attenuation we reach almost uh 5 DB almost 6 DBS of gain and then we attenuate down to minus5 uh so linear range if we were to pick any one of them and consider multiple uh samples as you can see uh the response is very well contained from sample to sample the bandwidth is about 30 gz and uh about Distortion these are the results of the single on measurement um obviously at the increasing frequency uh you experience a higher harmonic Distortion both the uh ht2 and ht3 are represented over here and again consistent sample to sample uh two ton measurements are are shown over here so same thing again inter modulation Distortion is been measured uh so um fairly flat as you can see in based on tone spacing and obviously uh getting worse for for higher and higher frequency and finally we also did evaluate this with modulated signals uh so you can see here uh 1024 quam a 5 gigahertz you can see the uh spectrum of the output uh it's uh it's very good uh a testament to the linearity and the 2048 quam again a 5 G for a 50 mahz bandwidth and so on so as a summary uh we effectively demonstrated uh to to be able to support uh with more functionality same similar power area of the um the the closest comparable uh but with uh three times the bandwidth uh then the closest comparables and uh we have a we have results here for for modulated signal uh so that's that's the summary and now let's go to the second problem The Continuous time uh pipelining as a way to deal with uh clock Jud so the first question one person that is maybe not not familiar with the problem could ask is you know how much Jitter is acceptable well the question of course the answer depends on what type of uh SNR the the church trying to achieve so for example if we want to achieve 60 DBS so we're talking about effectively 10 bits ADC uh and uh we're talking about if we're sampling a signal at 1 gigahertz what's acceptable well at the at at the minimum inverting this formula you should be able to get a sampl Jor with an RMS value of 160 ftoc uh so is it difficult to achieve well it is I mean it is and it's expensive in power so there was a recent publication from Professor bad RAV of UCLA that has shown that uh you know obviously when you have a j clock for a for a for an a2d this is going to degrade your SNR right so how do you read this plot well let's say that we wanted to achieve accomplish 10 bits res solution uh at at night Quist you know if we want to we don't don't want to have an impact this plot is saying that you should have a a juder that is a little bit less than um than uh here uh 10 uh 10 ftoc RMS uh which frankly is very hard to achieve these days so if you if you say well I'm going to compromise I'm going to accept accept the penalty of 1 DB then this plot tells you that the the J RMS should be really uh less than two sorry than 20 F to Second RMS and so on and so forth if you say well let me let me compromise 3D piece of uh uh of SNR well then then you can really go or you know pretty much up to almost 30 ftoc RMS but is is this expensive well it is because essentially this other plot shows you that for this demand of of dynamic range effectively uh if you accept the 3db of of penalty then uh you can probably uh have a viso that consume about 20 watts but if you say no I'm not going to accept 3db I want to accept 1db then then you're dealing with 300 M so that is a 15x jump only for or 2 DP Less in SNR penalty this is not negligible because as we will see you you may end up that you actually spend more power in your clock generation than the ADC itself so if there is something that can be done on the ADC to uh to mitigate to to to be able to uh to to to to work with a a moary clock that will save power of course on the generation so this is an example that I think is very emblematic this is the case again shown in this paper where you know if you have a 12bit 5 gz ADC uh this is an example was published a few years ago that consumes barely 160 Mills however if you want to have a only a One DB penalty for the clock your V would have to consume nearly 20 watts even if you say well I want only 3db of the gradation well still we're talking about five Watts so excellent ADC but if we really want to get the best out of it we really need to have a very very power consuming um uh clock generation so what can we do about it well the problem starts when you take the the sample so most ads they have uh the sample and all right right up front and so we can call this upfront sample and hold once you take the sample with the Jer The best scenario you can ever get of course is determined by the formula that we have already discussed after that uh the sample is taken and you can convert it so the question is what if we try to move this the the sampler from the front of the ADC sampler cells inside the ADC in which case you still are suffering of course from this degradation but perhaps depending where we move it we can have some mitigation so so let's see one architecture that is becoming U more common these days is the continuous time pipeline ADC um discrete time pipeline adcs are very well known and continuous time pipeline ADC are becoming more common but both uh of course share a pipelining architecture where uh uh each stage is going to determine the different uh bits uh representing the input so you start with the msbs and down all the way to lsbs so maybe the sampling instead of having it right here in front we can move it somewhere else in the chain where uh after after determining some of the msps the accuracy required for the remainder of the conversion has been relaxed so another advantage that uh continuous time pipeline adcs have is that they actually simplify the design or at the interface where the input circuitry drives the ADC because effectively continuous time pipeline adcs have an input uh that is uh effectively uh uh passive it's a it's it's not a switch cap circuit it is a continuous time circuit so it looks like a resistor or a resistor and a capacitor so it's easier to drive and um so let's look at one of these continuous sign pipel ADC so let's look at a very simplified case of a two stage where we determine uh the MSP in the first stage and then the output of the first stage it's a uh what is called a residue it's a what hasn't been already converted and now needs to be converted and it's passed to a second stage that determines the other bits so at a very high level this is a block diagram of that so what you have is that you have an input the input gets sampled by a sub a2d which is typically a flash a2d this determines the uh the most significant bits then this most significant bits are converted back into analog domain and subtracted from the input you add a delay in order to align in time the input with this quantized input and the difference of that is what is called the residue the residue now needs to be uh further converted to determine the other bits and that's typically done after some signal conditioning some amplification and then goes to the next a TOD which is nothing else often times than another stage like this or it could be any other architecture then you combine the two digital outputs in what is called a digital reconstruction filter and that combination gives the final output now this diagram is also showing a couple of more important things it's showing that when the sub Tod uh uh determines the MSP it's effectively sampling also the input so there is some Jitter degradation involved with that additional Jitter degradation happens because the d2a the sub d2a over here is is also controlled by the sampling clock so there will be impact at the output of the d2a and then finally over here if we put our Infamous sample and hold in front of the following stage then clearly there will be an additional degradation here so we have three main sources of jutter right here J adc1 affecting the FL sh right here the Jitter imposed to the uh to the duck and then finally the uh jutter on the remainder of the ad Tod so let's look at the contribution of these uh uh different sources of Jitter for starting from the juder of adc1 so the the a2d uh obviously uh this juder over here is going to affect the determination of the most significant bit however its impact is also propagated through the dock and finally to the back end of the ADC so by doing some some mat uh what you'll you'll see uh very simply is that effectively the impact of this juder can be cancelled and uh you can think of this uh uh it's well known with even with discrete time pipeline a to this many of the errors of the uh sub ADC are actually cancelled when the uh the the the bits that are determined by the different stages are recombined in order to obtain the final one so it's very well known that for example uh offset Happening Here can be uh can be uh corrected by the digital error correction and so on and so is the case here of Digit so this guy doesn't really count that much so that's good news uh let's look at the uh shape of the residue over here to understand the something else a little bit better so what I'm showing here is thein which is the the uh the blue curve or rather what I'm showing here is really the current after the delay line which is nothing else than the input after some delay so that's the blue curve it's continuous then here we uh quantize the input we Rec re bring it back into the analog domain and that's the I duck the current out of the duck that's essentially here as you can see the red curve is a quantized representation of the blue and then when you take the difference you get the residue which is this funky green curve uh which notice has a very high frequency content even just by inspection so when we look at that uh over multiple Cycles and having a relatively lower frequency input what you can see is that here the red curve which is the residue uh clearly is a it's it's a very high frequency zigzag curve so when we sample that on the back end the adc2 the stage two we're dealing with a very high frequency signal and as you remember the sensitivity uh due to jar is is uh determined by the by the frequency of the of the signal that you're trying to SLE so you can expect that the slope of this red signal is very very high and so that will be very sensitive uh so what we do is that we're going to filter this and uh uh by low pass filtering what what happens is that uh we are still going to be able to keep the important information which is really what needs to be still converted but but mitigate a little little bit the um the the high frequency content of the of the residue so we deal with a smaller slope so because of this reason now the the impact of the Jud of adc2 is the usual one that again we're sampling the the input we're at the output of the first stage uh it is the same as always however uh number one uh this has been reduced by inter stage gain of the first stage which uh if we resolve one bit is effectively a gain of two and uh um and then of course with the additional filtering we can for small signal we can have an additional reduction that depends on the effectively the ratio in of the frequencies between the input and the frequency of the residue what about the juder of the deck well unfortunately the juder of the dock cannot be mitigated so uh whatever the the the the DC will degrade will be sampled it will affect our our uh final output so the question is can we do something about the uh waveform of the dock and there are different waveforms that are possible for a for for a dck Return To Zero or a non Return To Zero Etc what we did is that we picked a non Return to Zero uh waveform uh and the impact of the on the SNR due to jiter uh because of the of a this Choice effectively is analogous to the one of a regular ADC although for different reasons uh but the important part is that we can actually uh uh improve that uh by uh increasing the oversampling of the output of the deck which by the way is very intuitive which basically means that if we make this this Jagged curve a little more continuous In Time by adding intermediate steps instead of having large steps uh then we make this more continuous and we make the slope more graceful which essentially translates into reducing the impact of Jitter so that's effectively what this formula is is saying and how do we accomplish that well instead of having a single to D in a single D way the clock of the Fest we're going to interleaf we're going to have uh two a2s and two d2a which are time interlift so effectively the section is effectively running at twice the sample rate and uh and then after that everything stays the same so obviously here the residue will have a higher frequency but also smaller steps and that mitigates the impact of this uh of this Jitter at the deck so if we have 2X the frequency over s through the over sample then we gain 3db of better gital tolerance that's not bad because remember that a difference in 3db can actually make the demand on the power of the VC dramatically lower dramatically lower remember that the 15x difference uh now of course if we inter leave there is a price to pay and the price to pay in our implementation is only an additional 25% in power on the ADC so instead of having an ADC that consume 200 Ms we have an ADC that consume 250 Ms that's a very tolerable price to pay if we are actually diminishing the demand on the on the vco 15 times so uh so that's uh that's something that we can we can accomplish with this architecture so these are measure results this is a die photo what I just described uh you can see the spectrum of the output there is uh the input tone over here we have an inter living uh artifacts the uh the noise floor is a little bit tilted because stage two here it's actually implemented with a vco ADC which is well known to have a um a first order noise shaping and so that's why you get this uh tilt on the on the noise uh measure results in terms of Peck SNR all the way to uh about uh almost 62 uh DPS uh we're looking at here an input that it is uh nearly 1 gahz uh sweeping the input signal frequency as you can see the SNR and the sfdr are fairly uh fairly flat and graceful um some other measurement I don't need to spend too much time here this is the plot that really demonstrate what we just accomplished which is basically if we had a a a a classic upfront sample a2d everything else being the same the SNR once reaching this red line would have started going down but we simply push this this limit quite a bit on the right and effectively gaining 3db or better SNR um uh mitigation here so as you can see the measure curve actually goes beyond that and uh all the way up to uh 500 ftoc RMS of juder uh actually can stay uh up and then obviously uh then this is when when you see the effect really of course of the uh second stage and the dock then of course it follows the the theoretical uh drop in in SNR comparison this is the work I just uh presented 16 nanometer implementation uh with a band input bandwidth up to one uh gigahertz uh uh and of course we have an ER aning this is one of the property of continuous time pipeline power area ETA uh the i' I've shown you that really this allows to um basically uh to sustain the SNR well beyond what was otherwise limited by an up front sampling which means a dramatic uh power saving overall for the entire system uh and uh uh here this work uh in uh is shown in the figure of Merit plot you can't have anything in a tods without without comparing yourself in the figure of Merit so is uh obviously accomplishing a respectable figure of Merit uh for the 1 gz input and so uh what I've shown is that the fundamental tradeoff between SNR and clar juder uh is obviously a severe limitation high frequency input signals uh but I have demonstrated that uh uh um this is accomplishable and uh and we can uh we can reduce uh by 3dp the sensitivity to clock Jer unlike the case of an up front sample and this is my presentation uh and I'm open for questions so so thank you very much Gabrielle for this very nice talk so uh please do your questions using the shat Channel I see no questions yet uh please do it the questions as soon as possible so um waiting for more question I have one uh can you comment about uh the tolerance to radiation effects on the adcs can I comment sorry can you the tolerance to radiation effects oh uh this was not intended to be a red hard chip uh and uh if you wanted to of course it comes down to the all the classical remedies uh uh you know uh ginging and uh redundancy for uh for digital parts of the chip but this was not intended to be a red hard chip so we didn't do anything special but there is nothing really specific to this architecture that would be good or bad in that sense okay so I have a question here by Luis D so he's uh he student at ufrgs so Mr Gabrielle manganaro you have been working on this area for a long time can you give an example of a solution that we use today in your daily life that is the result of your research well I mean if you go through my Publications there are a few things um improvements in Delta Sigma architectures in highspeed Ducks uh so you should just go through my Publications and patents and I I I I I think I did my part to to improve the state of the art especially in highspeed data converters so I'm not goingon to brag in public that's not me yeah so Louis you can see the publications of Gabrielle that you see a large set of uh achievements that uh were a result of the research and the work provided by Gabrielle no so another question here by FR Professor Fran Riv from University of bord IMS so this is a general questions can you expect to go really beyond the limits are there any hope or fyss will just limit us to continuous but harder and harder improvements well I think what I've just demonstrated is that the limits can be pushed uh and uh of course you cannot go beyond theoretical limits okay so uh for example example there is a there is a absolute limit on the figure of Merit on the power efficiency and we're getting closer and closer to that beyond that you know it's not going to be about the efficiency but I think that part of this talk uh was aimed to demonstrate that this is not about only the performance of of data converters you can have data converters that consumes a very little power and accomplish amazing performance but you really need to be able to use them so uh you need to look at the system as a whole there was a there was a fantastic keynote speech by Professor Bram na at the last assc where where he he provoked The Audience by showing that advancements in data converters are terrific but when you look at what's in front of them uh it's uh it's problematic and so that we should actually change our approach completely so um I I think I think the reality of it is that uh the demands that we get today for from applications particularly in communication and uh um in sensing areas are are really are really stressing the the the requirements for for data converters and uh so we we need we need to figure out how to how to meet these demands one way or another and obviously the price to pay is always going to be the same power consumption area cost uh but again uh as I tried with this talk uh to to express uh that's only half of the story you need to actually you need to look at the entire system get the input in and uh get a good um uh resilience from uh from Jitter and and so on yeah thank you so we have a question by shivaji Chi so great talk sir thank you very much if you want to design Secrets which work in the nanowatts range how to generate the bias current for these circuits okay this is not my field this is ultra power ultra low power I can tell you uh that obviously this type of circuits are working well into deeps up threshold uh it's an entirely different game and yes uh the biasing of this is is problematic because because uh matching uh matching is is not great and when you have mismatch between the bias in circuit and the main circuit and the the depend the sensitivity is exponential you have a big problem so I can't answer that question this is not my my area of expertise uh but uh this this are certainly serious problems okay thank you so um uh I see no more questions if someone has still a question you have to do it now so okay so I think we have to thanks now to Gabrielle manganaro for the excellent talk and the excellent work that he's doing so today we had uh the attendees that included their name here in the chat we have a well a large set of attendees from Brazil but also from Uruguay uh from Bordeaux France from USA from uh Al also Panama and uh but there is also some ones that uh don't put their names here in the shat and for sure we are going to have also a large set of attendees that will uh see the talk later no so thank you very much again Gabrielle for this excellent talk so the last question by shivaji was from uh uh IIT Bombay India [Music] know