hey everyone I'm Nick and this is bits of architecture so in this episode of the series we're going to be talking about our pipelined risk 5 architecture so in the previous videos we have talked a lot about pipelining right so we talked about what pipelining is and some of the difficulties that we run into related to these things called hazards so as a brief refresher on what pipelining is and you know why we're so keen on implementing it pipelining is this idea that we can break up our execution of our instructions and do individual stages so unlike our single cycle processors where we execute an entire instruction in a single cycle with our pipeline or multi-cycle processors we're executing uh one stage of our pipeline for an instruction every single cycle and because we've broken this up into stages we can overlap the execution of multiple instructions right so we can get better utilization out of these Hardware structures so while one instruction is doing say right back to the register file another instruction could be accessing memory another could be doing something with the ALU so in the execute stage another could be decoding an instruction and another could be uh you know actually fetching an instruction right from instruction memory so we can get all of this parallelism out of our instructions this overlap and see a pretty good performance Improvement now how exactly do we implement this pipeline processor right what is our high level architecture diagram look like well it looks something like this right something that's quite similar to what we had uh seen in the past for our single cycle implementation the only real major difference between our single cycle implementation and this one is these uh these these structures that are coming down dividing these different stages here so dividing instruction Fetch and decode dividing decode and execute dividing execute in our memory stage and our memory stage in our right backstage and these things we're going to call pipeline registers right now why exactly do we need these extra structures right these pipeline registers well recall the main difference between pipelining and our single cycle processor with our single cycle processor an instruction has access to all of the hardware resources in a given cycle right so it can access instruction memory read the registers do some sort of execution maybe do something with data that the data memory so maybe a read or write and then of course again right back to the register file right all within the same cycle we no longer have that with our multi-cycle implementation an instruction is only allowed to work within a single stage of our pipeline at any given moment right so by the time we're in the execute stage of an instruction right that instruction no longer has access to things from the decode stage right so um you know say the values we read out of a register file in the decode Sage have to be saved somewhere for use in the next stage right so for example if we had an R type instruction doing say an ad so in the decode stage that instruction would read up the two registers that it wants to operate on and it would save them in this pipeline register right that way in the next cycle it could then use those values from pipeline register in the execute stage while another instruction say I2 reads out the registers that it wants to use right out of the register file right so we need these pipeline registers in order to checkpoint the state for instructions as it moves through the pipeline so these pipeline registers just keep track of everything that instruction needs as it goes through the pipeline so one thing that's kind of omitted from this diagram and is something that we'll we'll end up doing from time to time in order to simplify this diagram so we can look at it and understand it a bit easier um is uh we're missing the control lines from this diagram so how are these different uh Hardware units controlled they're still controlled with the same kind of control lines that we had in the past so a register file still has this register right flag our multiplexers still have these flags for say selecting an ALU Source whether that's an immediate value or that's coming from you know a register or data memory has our memrite and our memory we have say a branch flag so whether or not this is a brand instruction so all of these flags still exist but recall we have a bit more challenging than issue now right so just like our state like you know the values from a register need to be saved in a pipeline register the same is true for our control signals right um You Know Each instruction might have a slightly different set of control signals um to um you know orchestrate these different Hardware structures right so the control signals that you know a load or a store instruction needs is going to be different than say an r-type instruction right for something like a a store right we have to set this mem right signal but for a you know just to add we don't need to set mem right at all right we don't care about the memory stage so we also need to do some checkpointing related to these control signals as an instruction moves through the pipeline so that's also what our pipeline registers are going to do they're going to help us keep track of these control signals so you know recall as we went through with our single cycle processor we have a control unit that takes in our instruction right or our op code and it's going to generate control signals based upon what operation that we're going to perform and it'll send these different control signals it'll save them rather inside of our pipeline registers so that they can be used in the stage that they're needed right so we have two signals that are needed in the right backstage three signals needed in the memory stage and two signals needed in the execute stage so if we go ahead and go back to our original diagram right we can even see those signals so um you know after uh you know decode here where we're decoding our instructions and setting our control signals inside of the execute stage we have our two signals we need which is for multiplexer or ALU source as well as our ALU op control signal that helps us control what operation ALU is going to perform so there's our two control signals for execute inside of our memory stage we have three signals right so we have memory to MIM right so controlling whether we're doing a read or write and then we also have a branch signal here um that's that you know is there to select our next program counter value we're not going to count this uh the zero control signals coming out of our ALU here because that's not coming out of the control unit but it is another control signal that we'll save in the pipeline register but this one's not uh coming from our control unit back in the decode stage and then in a right backstage right we have two control signals one selecting our mem to Reg source so what are we saving to a register file something from data memory or are we saving something from our ALU that we calculated right so we're selecting between those two and then of course um the other signal that we have in our right backstage is our register right signal so whether or not we're going to write to the register file right so remember not every instruction writes to the register file a branch of equal doesn't write to the register file neither does a store instruction that doesn't write to the register file um okay so those are the signals that we need to keep track of here right in these pipeline control registers so let's kind of put it all together right so we can put everything into one diagram uh even though for the most cases we'll omit some of these control signals so we can focus on maybe some of more uh interesting Hardware structures that we're looking at at a given moment so this is roughly what it will look like and to simplify it somewhat instead of doing all seven control signals I've just grouped uh right back MIM and execute signals into just a single line here or rather one for each right for Simplicity so you can see in the decode stage right we get our instruction our op code we set our control signals and those get saved inside of the pipeline register then when they're needed so in the next stage and execute when our execute signals are needed those are piped down into the hardware structures so into our multiplexer into our and our ALU control unit then in the memory stage we get our memory signals for our Branch our memrite and our mem read and then in the right backstage we get our signals for our multiplexer and for our um are register right here for our register file so whether or not we're going to be writing to the register file okay so that's going to be the basics of our risk 5 pipelined architecture so in many ways it's similar to our our single cycle implementation right many of our structures are exactly the same like our our multiplexers or program counters or memory our registers or alus Etc the main difference is that we now have these pipeline registers though to keep our checkpointed state as an instruction goes through these different pipeline stages in later videos we'll talk about how we handle some of the other interesting details like forwarding and bypassing inside of this architecture as well but that's going to go ahead and do it for this time as always I'm Nick and hope you have a nice day