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Understanding Gate Level Modelling in Verilog

Sep 4, 2024

Gate Level Modelling Lecture Notes

Introduction

  • Discussion on gate level modelling
  • Four levels of design description:
    • Gate Level (Structural Level)
    • Circuit Level (Switch Level)
    • Data Flow Level
    • Behaviour Level
  • Gate level modelling is easier for digital designs.

Gate Level Modelling

  • Uses primitives of combinational logic gates:
    • Basic Gates:
      • NOT Gate (Primitive: NOT)
      • AND Gate (Primitive: AND)
      • OR Gate (Primitive: OR)
      • NAND Gate (Primitive: NAND)
      • NOR Gate (Primitive: NOR)
  • Approximately 26 primitives available in Verilog library.
  • Describes interconnections of wires between gates.

Input Characteristics

  • Combinational gates can have n inputs, where n varies:
    • NOT Gate: n = 1
    • AND/OR/NAND/NOR Gates: n ≥ 2
  • N output primitives (multiple outputs) available:
    • Examples:
      • Buffer (buf)
      • Tri-state Buffer (tri)

Buffer Types

  • Two-State Buffer:
    • Takes 0 or 1 states.
    • Acts as a current amplifier for larger loads.
  • Tri-State Buffer:
    • Has three states controlled by a control signal (C):
      • If C = 1, output = input
      • If C = 0, output = high impedance state (Z)
  • Fan Out:
    • The number of devices connected to a single output.
    • Example: If output can provide 10 mA and each device requires 1 mA, fan out = 10.

Verilog Code Examples

AND Gate Example

  • Syntax for two-input AND gate in Verilog: and (output, input1, input2);
  • Input combinations and logic output for an AND gate:
    • Inputs: A, B can be 0, 1, x (don't care), z (high impedance).
    • Output derived based on combinations.

Verilog Code for AND-OR Inverter Circuit

  • Circuit description:
    • Inputs: A, B, C, D
    • Output: Y
  • Example Verilog code structure: module AOI4 (output Y, input A, B, C, D); // Define wires wire w1, w2; // AND Gates and (w1, A, B); and (w2, C, D); // OR Gate and Inverter or (Y, w1, w2); endmodule

Design Steps for Combinational Circuits

  1. Define the problem based on specifications.
  2. Assign letter symbols to inputs and outputs.
  3. Draw a truth table.
  4. Write Boolean expressions for outputs and simplify (KMAP).
  5. Draw the logic diagram.

Example: 3-Bit Squarer

  • Input: 3-bit (A2, A1, A0)
  • Output: 6-bits (Y5, Y4, Y3, Y2, Y1, Y0)
  • Truth table for input-output combinations established.
  • Example Verilog code structure to square 3-bit input: module Squarer (output [5:0] Y, input [2:0] A); // Logic implementation endmodule

Conclusion

  • Verilog is useful for describing circuits and testing their functionality.
  • Upcoming classes will cover more examples on combinational circuits.

Thank you for attending the lecture!

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