Understanding Gate Level Modelling in Verilog

Today, we will discuss about the gate level modelling. As we know that there are four levels of design description. Take the design description. This can be done by using four ways. So one is gate level, this also is called as a structural level. Then we have the circuit level, this also is called as switch level. and we have the data flow level and behaviour level. So, out of these four, so this gate level description is relatively easier to describe the design. Basically all will be used to describe the digital designs. So, first we will start with this gate level modelling. So, in gate level modelling, so this basically uses the primitives of all the logic gates. Primitives of all the combination logic gates are used to describe the design. So, what are the basic combinational logic gates such as NOT gate, you have a primitive with NOT, you have AND gate, AND, you have OR gate, OR, NAND gate, NAND. NOR gate, NOR. So, they are already available in the VLS, I mean Verilog library. So, there are nearly 26 different primitives are available, are available in Verilog library. So, this not only uses this logic gates, but also in addition to this, this also describes the interconnections of the wires. So, if the different amine primitives of Verilog, or not, and, or, and, these are all n input primitives. So, here n varies from 1 to any value. If I take not gate n is equal to 1, for and gate you can have any value of n, for or gate also, and gate, nor gate, so n is, n can be greater than or equal to 2. So, minimum 2 inputs are required, this is greater than or equal to 2. So, there are some primitives which will be having multiple outputs. N output primitives such as you have buffer buff and you have buffer if 0, buffer if 1. So, this can have the multiple outputs. If you take a simple buffer, the symbol of buffer is same as the NOT gate or inverter except for the bubble at the output side. So, this will have some input, some output. In terms of the voltages, is equal to input. If you give the logic 0, 0 volts, output is also 0 volts. If you give 5 volts as the input, output is also 5 volts. Then what is the need of the buffer? So, buffer is basically this will acts as a current amplifier. So, if want to drive the large current capacity loads, so normally we will use buffers. So, this is just a two-state buffer, we can call this one as a two-state buffer. It can take only two states. So, states are 0 or 1. So, there are some buffers which are called as a tri-state. This is tri-buffer if 0, tri-buffer if 1. So, the difference between the tri-state buffer and a two-state buffer is as the name implies in tri-state buffer we have three states. So, this is a buffer in addition to this we have one control signal, this is control signal, this is input and output. So, the operation is if C is equal to 1, implies output is input. If c is equal to 0, output will becomes a state called high impedance state z, z is high impedance state. That means, if I want to connect this to some device, this will offer a high impedance path, the resistance of this wire will become high impedance. As a result of that, this will act something like a open circuit, almost like open circuit, so that this does not draw any current. As a result of that, we can increase the current capability of the output of this particular gate. So, this is if c is equal to 1, output is input, c is equal to 0, output is z, this type of buffer is called tri buffer tri if 1. If I place a bubble here, means the operation is reverse to this one. If c is equal to 1 high impedance state, c is equal to 0, output is equal to input. This type of buffer is called try-if-0 buffer. So whether you take a two-state buffer or tri-state buffer, they can have multiple outputs, n output primitives. How they can control this multiple outputs is, so we can connect output of this particular gate. Suppose if I take this output, output of this particular this can be connected to many devices. This is device 1, this is device 2. Who is going to control this number of devices that can be connected to a single output? Suppose if you have this is 10th device, this is what is called fan out. You might have studied in your digital logic course. So, if the current required to drive this one is say 1 milliamps. This is also 1 milliamp. If I assume that all belong to same family, this is 1 milliamp. If this output is capable of giving 10 milliamps of the current, then I can connect 10 of these devices which draws 1 milliamps of the current, then fan out is called as 10. So, depends upon the current capacity of these devices and the current that is supplied by the output of a gate we can connect multiple So, this is what is called n output primitive, this n is nothing but the fan out. So, like that we have 26 different primitives in Verilog library. So, coming for our basic circuits, if I take a simple AND primitive, AND gate. Because, any digital circuit can be implemented by using these basic gates such as NOT, AND, OR. Using these three gates, you can construct the remaining gates such as NAND, NAR, exclusive OR, exclusive NAR and so on. So, the basic, the primitive of this one is, you have to use lowercase letter, very large is a case sensitive language. So, you have to write only lowercase letters AND. So, within the bracket you have to represent first the output. So, output will be normally only one for the AND gate, we can have any number of the inputs. Suppose if you have 8 inputs, i1, i2, say i0, i1 so on up to i7. So, this will represent an AND gate whose output is O, whose inputs are i1, i2, i2, i3, i3, i4, i5, i6, i7, i7, i8, i9, i9, i10, i11, i0, i1 so on up to i7. So, instead of writing this, you can simply write using this primitive and with this output followed by input. So, now if I take the two input and gate, say a and b are the inputs, y is the output, y is given by ab. So, here each value A can take 4 different values here, this is A, this is B. So, A can take either 0 or 1 or it can be x which is a do not care, it can be z which is high impedance state, this is do not care, this is high impedance state. I have already discussed what is meant by high impedance state means it basically draws almost 0 current. Similarly, B can take 0, 1, x and z okay. So, what are the output value y for different combinations? So, we know the ordinary combinations like 0 0 output is 0. If any one input is 0, output will be 0. So, if b is 0 regardless of a whether this is 0 or 1 or x or w, output is 0. Similarly, when a is equal to 0, regardless of b, b is 0, 1, x or z, output will be 0. So this row and this column both are 0s. Now for 1, 1, output is 1, 1, x, output is x, 1, z, here there is a logic 1, z is also x. So, the reason for this one is suppose if I have an input which is floating, I can connect this input to either ground, I can connect this input to Vcc which is plus 5 volts. So, in this case, this is logic 0, this is logic 1. Suppose if an input of the gate is floating, So, I have connected here logic 1 5 volts, this I have not neither I have connected these two 5 volts nor I have connected these two ground, this is floating. So, this is what the meaning of Z, Z is high impedance state this is almost open circuit type of thing. So, it is coming from some other gate, but this is almost open circuit. So, when a gate is floating, so normally in NAND logic if input is floating, floating input will be taken as logic 1 in case of TTL gates transistor-transistor logic. Whereas, the floating gate in CMOS logic is a do not care, because this is going to mean on both the NMOS and PMOS transistors thereby the circuit oscillates. So, if floating input is there in CMOS, this CMOS causes CMOS circuit oscillates. In TTL it is usually taken as 1 whereas in CMOS this will oscillate means do not care basically. So, if one input is 1, z in case of this I mean a TTL gate, this is the input 1, but normally we use CMOS gate because the circuit oscillates, so this will be taken as a do not care, so that is why this will be do not care. If one input is 1, other input is z, this will be taken as a do not care. So similarly x1 is x, xx is also x, xz is also x. So, 0, z0 is 0, z1 is x as we have discussed earlier like here we have z1 is x and then we have zx is also x, zz is also x. So, this is the logic operations of AND gate for all combinations of the inputs. Similarly, you can have for OR gate, the other gates also, AND, NOR and remaining gates. So, now using these basic gates, how to write a Verilog code? So, I will discuss a Verilog code for a simple circuit. called AND-OR inverter 4 input circuit. This is AND-OR inverter 4 input circuit. As we have discussed this Verilog has a twofold operation. Verilog can be used for Describing the hardware given a circuit, we can describe by using the keywords. We can describe the circuit or we can test the designed circuit. First, I am going to explain with an example how This Verilog code can be used for describing a circuit. The circuit that I have taken is AY4 means this is something like we have 4 inputs, 2 inputs for this AND gate, 2 inputs for this AND gate A, B, C, D. Then we have R gate and inverter, I am going to club these two together so that this becomes an R. Basically, we have AND gate, R gate, NOT gate, inverter, AY. These four represent four inputs. Output letters call as Y. So, I want to describe this instead of drawing this diagram, I want to describe by using Verilog code. So, how to write the Verilog code? So whatever the code that you have to write, we have to write between the module and end module. So, the starting this one is module, you have to give some name. So, I am giving the name of the module as AOI4 itself. After reading the program, the last keyword is end module. So in between this, so whatever the description that you have to write. So, AOI followed by here you have to specify the inputs and outputs of the circuit. So, we have one output and four inputs. First you have to specify output Y. Then the inputs a, b, c, d, so after that we require a semicolon here. Then you would describe what are these values, output y semicolon, input you have a, b, c, d semicolon. So, this instead of writing these three I mean keywords, this can be described in a single keyword also like module is same, the name is also you can write the same name ay4. So within this bracket, here itself you can write output y comma input y comma input y have to give some tab, here you have to give the gap between after this output or after this input, a comma b comma c comma d. So, this single keyword is equivalent to these three. So, you can write anyway. So, I am using this notation only. So, this definition of the input and output ports also you can give here itself. Now, coming for this one. So, we have four input ports. This will be connected to the input port and this will be connected to the output port. In between if want to interconnect these gates, We require some wires. This is similar to the physical connection that you are going to give in a digital laboratory. So, I want to connect the output of this AND gate to the input of this NOR gate. So, I require a wire, I will call this one as W1. Similarly, here also I require another wire W2. So, you have to define this wire. Wires are basically easy to connect. the gates in the design, wire w1 comma w2 semicolon. Now, I can give some name for this AND gates and OR gates. So, this I will call as A1, this I will call as A2, this I will call as N2. You can directly give this as an OR or you can give OR and NOT also, this is up to you. So, I am writing this primitive of the undecati as I have discussed in the earlier slide is and lowercase and. And in the parentheses, you have to first write the output, which is w1 and you have to give the name because there are two AND gates to distinguish between these two, you can write a name. So, I am defining this AND gate as a1, for a1 what is the output w1 comma, the inputs are a comma b. Similarly, there is second AND gate a2, a1, a2, a1, a1, a1, Output is w2, the inputs are c and d. Now the final output y will be the output of the NOR gate. So you can write directly NOR whose output is y, the inputs are w1 and w2. This w1, w2 you can write in any order. So, that is all. This is the description of this given circuit which is called as and R and inverter circuit. So, you can also write this NAR as otherwise, this you can write using two, I mean, keywords. One is you can use R with the, so you have to define one more wire here. If you want to write this NAR as the inputs are w1, w2 and this is y, this is equivalent to R followed by you can define another w3 in that case you have to define here another w3. gate, this is finally is y. So R, so you have tried here w3 in that case, output is w3, w1, w2 semicolon not y, w3. So this is how if you write this program, this will give you the description of the given circuit. So, this is I mean Verilog is having twofold uses. One is it will describe the circuit. So we can test the designed circuit. So, you have some design. So, normally how to test the design? Normally, you will connect using the ICs and I will test the functionality. So, whereas using Verilog code, you can test the functionality of the design by writing the Verilog code. So, I will consider another example of how to I mean test the design. So, for that I have to first discuss how to design the digital circuit. We know that digital circuits can be broadly classified as. combinational circuits and sequential circuits. So, combinational circuit is a logic circuit where the output at any time depends upon only the present input without regard to the previous outputs. Whereas, in case of sequential logic circuits, the output not only depends upon the present input, but also on the previous outputs. So, you need some memory in case of sequential to remember the previous output. So, this requires some memory and there will be some feedback connection from output to input. So, first I will discuss the design of combinational circuits and the corresponding Verilog codes. CKT is the symbol for the abbreviation of circuit. So, there are certain rules for design of combinational circuits. So, step 1 for the design of the combinational circuit is, so you have to define the problem. From the specifications, determine, so you will be given the specifications, determine the number of inputs available and the number of outputs required. Then step 2 is assign letter symbols to all the inputs and outputs. Third step is draw the truth table which describes the relation between the input and output. Then next step is write the Boolean expressions for all the outputs. outputs and simplify by using KMAP and next step is this is the last step draw the logic diagram. Once the logic diagram is obtained to check the functionality normally we will connect. using the ICs. For a simple circuits which contains less number of gates, you can test manually. But in case of VLSI circuits where millions of the gates are there, then you have to go for the computer aided designs. So, here in order to test this logic diagram that we have obtained from the design, so you can write a Verilog code and you can run the simulation. You can give the different combinations of the inputs and you can check the outputs. So, in order to explain this design rules or design steps, I will take an example of a 3 bit squarer. So, the problem statement is given, how to obtain the logic diagram which I mean squares the 3-bit input value. So, the first step is how to determine the number of inputs available, is already given that 3-bit. So, number of inputs are 3. Then how to find out the number of outputs required? So, basically this circuit has to square the input number, you have 3 bits, say you have a2, a1, a0 is the 3 bit number, this is 3 bit square, so how many outputs are required? How to find out this? So, what is the maximum 3-bit number? So, the maximum 3-bit number is all the a2, a1, a0 should be 1, 1, 1. This is in binary, this is 7 in decimal. If I square 7, then I get what is the value? 49 is the decimal value. Sorry, this is decimal 1, 0 stands for the decimal base. So, what is the binary equivalent of 49? So, so many bits are required. at the output because you have to accommodate the maximum possible value also. So, 49 if you convert into binary 24 0 1, 2 12 0 0, 2 6 0 0, 2 3 0 0, 2 1 0 0 1. 2 0s 1. Until the quotient is 0, you have to stop here and you have to read this value from bottom to top. So, what is that value? Is 1 1 0 0 1. If you want to verify, you can verify also the weight of this one is 1 in decimal, this is 2, this is 4 parts of 2, this is 8, this is 16, this is 32. So, basically you are adding 32 because 1, 32 plus 16 which is 32. is equal to 48 plus 1 is 49. So, this in binary form is 1 1 0 0 0 1 in binary. So, we require 6 outputs. So, 6 outputs are required. So, starting with y 5, y 4, y 3, y 2, y 1, y 0. I am assigning the letter symbols. I am finding this one. The second one is I am assigning the letter symbols. I am assuming that a2, a1, a0 is the… This is second step also I have combined this. Step 1 and step 2 I have combined together. So, I have sent the letter symbols for the inputs as a2, a1, a0 and outputs as wi-fi to y0. Wi-fi is the MSB, y0 is the LSB. Wi-fi I have called as MSB. You have to clearly define this, y0 is LSB. MSB stands for most significant bit, LSB stands for least significant bit. The third step is you have to draw the truth table. For all the combinations, how many combinations are there because inputs are 3, a2, a1, a0. So, we have 8 combinations. Outputs are 6. So, y5, y4, y3, y2, y1, y0. So you take all the 8 combinations 0 0 0, so you found you can write the decimal value also here, decimal input value, decimal output value so that we can easily understand this problem, decimal output, decimal input. So, 0 means 0, 0 square, what is the decimal equivalent value? 0 only. So, what is 6 bit equivalent of 0? All 0s. Decimal 1, if the input is decimal 1, the representation in input binary is 0 0 1. 1 square is decimal is also 1. How to represent 1 using 6 bits? 0 0 0, 0 0, 1. If the input is 2, the binary representation of 2 is 0 1 0. So, the decimal square of this one is 4. So, how to represent 4? 0 0 0, 1 0 0. If the decimal value is 3, the binary representation is 0 1 1, 3 square is 9, how to represent 9? 0 0 1 0 0 1, these are basically the weights you can add. This weight is 1 2 4 8 16 32. So to get 9, you have to add 8 plus 1, 4 1 0 0. So, this is basically 16, 16 is directly there. So, 0 1 0 0 0 0, 5 1 0 1, 5 square is 25, to get the 25 it is 16 plus 8 is 24 plus 1. So, 0 1 1 0 0 1, 6 is 1 1 0, 5 1 1 0 1, 6 square is 36, 32 plus 4, so 1 0 0 1 0 0, 7 1 1 1, 7 is 49, we have obtained this. 32 plus 16 plus 1. So, you see the truth table. So, which will describe the given problem. For all the combinations of the inputs, it will give the output square value. So, what is next step? Step 4 is You have to obtain the Boolean expressions for the all the outputs and you have to simplify by using KMAP. You can see that one, even if you simplify also you will get same thing, y naught is nothing but this is 0 1 0 1 0 1 0 1, a0 also 0 1 0 1 0 1 0 1. So simply y0 is equal to, this is by observation, you can do it by using KMAP also you will get same thing, this is by observation. And y1 is always 0, y1 is always 0 and y2 is what are the minterms? y2 is sigma m. So, wherever Boolean expression you have 1, this 1 is correspond to this minterm 2, 2, this minterm is 6. You can use the K map. Basically, the inputs are, a2, a1 this is up to you can write in any way. I am writing a2, a1, a2 is MSB, a0 is LSB or you can write a2, a1 here and a0 here. So, in any case you will get the same final expression. So, we know that we are going to use gray code to number the rows and columns 0, 0, 0, 1, if it is binary 1, 0, 1, 1, if it is a gray 1, 1, 1, 0. So, this box number is 2, 2 means 0 1 0, 0 1 0 is this is 2 and 6 is 1 1 0, 1 1 0 is this, this is 2 box combination. So, therefore, y 2 is equal to. So, here the variable that is changing will get cancelled, a2 is 0 here, a2 is 1 here, so a2 will get cancelled, a1 is constant at 1, so you have to take without complement, whereas here a0 is 0, so this is a0 bar a1. Similarly, you can get y3 as sigma m is the min term is 3, 5. So, this is a2, a1, a0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 3, 5, 0, 1, 1 is 3, 5 is 1, 0, 1. So, you see nothing but just there is no mean combination at all this is single box combination, this is single box combination. So, you will have y3 is equal to this expression is a2 bar a1 a0 plus this one is a2 a1 bar a0. So, a0 is common you can write this one as this is y3. This is equal to A naught is common then it is exclusive or between A2 and A1. So, A naught times A2 exclusive or with A1, y4 sigma m mean times are 4, 5, 7. So, 0 0 0 1 1 1 1 0 0 1 a 2 a bar a naught. So, 4 5 7 1 0 0 5 is 1 1 1 0 1 7 is 1 1 1. So, these are two box combination, this is another two box combination. So, therefore, y 4 is this expression is a naught will changes. So, this is a 2 a 1 bar. and this one is a naught and here a2. So, a2 is common and similarly y5 is equal to sigma m67. So, if you simplify this, you will get 00011110 a2 a1 a naught. 6 7 1 1 0 1 1 1. This is a two box combination. This is simply Wi-Fi is A2 A1. So, these are the final expression, then we have to draw the Boolean, the logic diagram. So, I will draw here the expressions for y0, y1, y0 is a0, y1 is 0, y2 is, y2 we have got this y2 as a0 bar a1, y3 is A2 exclusive or A1, y4 is A2 into A1 bar plus A naught, A2 into A1 bar A naught and y phi is A2 A1 right. So, the last step is you have to draw the logic diagram. So, you can draw this logic diagram using gates. Now, synatom in write the Verilog code correspond to this one, module Using this Boolean expression directly I am writing the Verilog code or otherwise you can draw the logic diagram so that it will be easier. So this will be y naught is a naught, you have 3 inputs a naught, a1, a2 and the corresponding complements. You see how you can draw the logic diagram easily. You have a naught and if I connect through the naught gate a naught bar. This is a1, if you connect the not gate between this, you will get a1 bar, this is a2, this is a2 bar, so you have a not gate. So to get this is a0 directly you have to connect this from the a0, this is your y0. So y1 is basically ground, y2 is a0 bar a1, a0 bar line is this. A1 is this, this is y2, y3 is A0 into A2 exclusive or A1, A2 line is this, A1 line is this. This is exclusive R and this you have to end with a naught. This is your y3 and y4 is a2 into a1 bar plus a naught. a1 bar is this plus a naught is this R operation and you have to end with a2. This is A2 and Wi-Fi A2 A1. This is the complete design of this one. If you want to verify this normally we will in manual mode we will connect the ICs correspond to all the logic gates and we will verify. Whereas in Verilog code, if you want to write Verilog code, module, I will give the name as square R, output is y0 so on up to y1, y2, y3, y4, y5 comma a2, a1, a0 semicolon output. y0 comma y1 comma y2 comma y3 comma y4 comma y5 semicolon input a2 comma a1 comma a naught semicolon. Then how to get output y? y naught is same as a1, for that you can write buffer. buffer because buffer will give the same output is equal to input, buffer with output as y naught input as a naught and y 1 is 0, you can directly give assign y 1 is equal to 0. is 0 or we can give, if want to use a gate then you can use something like AND y1 inputs if you give any input like a2 comma a2 bar, if I give 0 say other input. This is up to you can design in many ways, you can assign directly in case of behavioral modeling. I will discuss that in the coming classes, this is 0, a2 comma 0. Then y2 is nothing but, so y2 you want a0, first you obtain this a0 bar, a1 bar, a2 bar using three NOT gates, NOT, so you call this one output as a0 bar, a0, NOT. bar, sorry a1 bar a1, not a2 bar a2. Then y2 is AND, AND y2 comma inputs are a0 bar a1, a0 bar we have already obtained. And, y3 is, you have to first, we have to define the wire here, we have to define wire y1, w1. So, xr, xr, output is w1, the inputs are a2 and a1. Then, we have to use end operation, end, output is y3, the inputs are w1 and then a0. Then y4, first you have to write R between A1 bar and A naught, this output you call as yw2, so w2 comma, the inputs are A1 bar comma A naught, then AND between output is y4, input is w2 comma, the other input is A2. and Wi-Fi is AND between A2 and A1, output is Wi-Fi A2 comma A1 and module. This is the complete design using Verilog. So if you run this program and if you simulate this A0, A1, A2. a naught, this you can give 0 or 1, this you can give 0 or 1 using the simulation tools and you can observe these outputs y5 to y0, y5 to y0, it has to satisfy the truth table that I have written in the previous slide. This is how you can check using this Verilog code. This is all about this first design. So, in the coming classes, we will discuss some more examples of the combinational circuits. Thank you.

Today, we will discuss about the gate level modelling. As we know that there are four levels of design description. Take the design description.

This can be done by using four ways. So one is gate level, this also is called as a structural level. Then we have the circuit level, this also is called as switch level.

and we have the data flow level and behaviour level. So, out of these four, so this gate level description is relatively easier to describe the design. Basically all will be used to describe the digital designs.

So, first we will start with this gate level modelling. So, in gate level modelling, so this basically uses the primitives of all the logic gates. Primitives of all the combination logic gates are used to describe the design.

So, what are the basic combinational logic gates such as NOT gate, you have a primitive with NOT, you have AND gate, AND, you have OR gate, OR, NAND gate, NAND. NOR gate, NOR. So, they are already available in the VLS, I mean Verilog library.

So, there are nearly 26 different primitives are available, are available in Verilog library. So, this not only uses this logic gates, but also in addition to this, this also describes the interconnections of the wires. So, if the different amine primitives of Verilog, or not, and, or, and, these are all n input primitives. So, here n varies from 1 to any value. If I take not gate n is equal to 1, for and gate you can have any value of n, for or gate also, and gate, nor gate, so n is, n can be greater than or equal to 2. So, minimum 2 inputs are required, this is greater than or equal to 2. So, there are some primitives which will be having multiple outputs.

N output primitives such as you have buffer buff and you have buffer if 0, buffer if 1. So, this can have the multiple outputs. If you take a simple buffer, the symbol of buffer is same as the NOT gate or inverter except for the bubble at the output side. So, this will have some input, some output.

In terms of the voltages, is equal to input. If you give the logic 0, 0 volts, output is also 0 volts. If you give 5 volts as the input, output is also 5 volts. Then what is the need of the buffer? So, buffer is basically this will acts as a current amplifier.

So, if want to drive the large current capacity loads, so normally we will use buffers. So, this is just a two-state buffer, we can call this one as a two-state buffer. It can take only two states. So, states are 0 or 1. So, there are some buffers which are called as a tri-state.

This is tri-buffer if 0, tri-buffer if 1. So, the difference between the tri-state buffer and a two-state buffer is as the name implies in tri-state buffer we have three states. So, this is a buffer in addition to this we have one control signal, this is control signal, this is input and output. So, the operation is if C is equal to 1, implies output is input.

If c is equal to 0, output will becomes a state called high impedance state z, z is high impedance state. That means, if I want to connect this to some device, this will offer a high impedance path, the resistance of this wire will become high impedance. As a result of that, this will act something like a open circuit, almost like open circuit, so that this does not draw any current.

As a result of that, we can increase the current capability of the output of this particular gate. So, this is if c is equal to 1, output is input, c is equal to 0, output is z, this type of buffer is called tri buffer tri if 1. If I place a bubble here, means the operation is reverse to this one. If c is equal to 1 high impedance state, c is equal to 0, output is equal to input.

This type of buffer is called try-if-0 buffer. So whether you take a two-state buffer or tri-state buffer, they can have multiple outputs, n output primitives. How they can control this multiple outputs is, so we can connect output of this particular gate.

Suppose if I take this output, output of this particular this can be connected to many devices. This is device 1, this is device 2. Who is going to control this number of devices that can be connected to a single output? Suppose if you have this is 10th device, this is what is called fan out. You might have studied in your digital logic course.

So, if the current required to drive this one is say 1 milliamps. This is also 1 milliamp. If I assume that all belong to same family, this is 1 milliamp.

If this output is capable of giving 10 milliamps of the current, then I can connect 10 of these devices which draws 1 milliamps of the current, then fan out is called as 10. So, depends upon the current capacity of these devices and the current that is supplied by the output of a gate we can connect multiple So, this is what is called n output primitive, this n is nothing but the fan out. So, like that we have 26 different primitives in Verilog library. So, coming for our basic circuits, if I take a simple AND primitive, AND gate. Because, any digital circuit can be implemented by using these basic gates such as NOT, AND, OR.

Using these three gates, you can construct the remaining gates such as NAND, NAR, exclusive OR, exclusive NAR and so on. So, the basic, the primitive of this one is, you have to use lowercase letter, very large is a case sensitive language. So, you have to write only lowercase letters AND. So, within the bracket you have to represent first the output.

So, output will be normally only one for the AND gate, we can have any number of the inputs. Suppose if you have 8 inputs, i1, i2, say i0, i1 so on up to i7. So, this will represent an AND gate whose output is O, whose inputs are i1, i2, i2, i3, i3, i4, i5, i6, i7, i7, i8, i9, i9, i10, i11, i0, i1 so on up to i7. So, instead of writing this, you can simply write using this primitive and with this output followed by input.

So, now if I take the two input and gate, say a and b are the inputs, y is the output, y is given by ab. So, here each value A can take 4 different values here, this is A, this is B. So, A can take either 0 or 1 or it can be x which is a do not care, it can be z which is high impedance state, this is do not care, this is high impedance state.

I have already discussed what is meant by high impedance state means it basically draws almost 0 current. Similarly, B can take 0, 1, x and z okay. So, what are the output value y for different combinations? So, we know the ordinary combinations like 0 0 output is 0. If any one input is 0, output will be 0. So, if b is 0 regardless of a whether this is 0 or 1 or x or w, output is 0. Similarly, when a is equal to 0, regardless of b, b is 0, 1, x or z, output will be 0. So this row and this column both are 0s. Now for 1, 1, output is 1, 1, x, output is x, 1, z, here there is a logic 1, z is also x.

So, the reason for this one is suppose if I have an input which is floating, I can connect this input to either ground, I can connect this input to Vcc which is plus 5 volts. So, in this case, this is logic 0, this is logic 1. Suppose if an input of the gate is floating, So, I have connected here logic 1 5 volts, this I have not neither I have connected these two 5 volts nor I have connected these two ground, this is floating. So, this is what the meaning of Z, Z is high impedance state this is almost open circuit type of thing.

So, it is coming from some other gate, but this is almost open circuit. So, when a gate is floating, so normally in NAND logic if input is floating, floating input will be taken as logic 1 in case of TTL gates transistor-transistor logic. Whereas, the floating gate in CMOS logic is a do not care, because this is going to mean on both the NMOS and PMOS transistors thereby the circuit oscillates. So, if floating input is there in CMOS, this CMOS causes CMOS circuit oscillates.

In TTL it is usually taken as 1 whereas in CMOS this will oscillate means do not care basically. So, if one input is 1, z in case of this I mean a TTL gate, this is the input 1, but normally we use CMOS gate because the circuit oscillates, so this will be taken as a do not care, so that is why this will be do not care. If one input is 1, other input is z, this will be taken as a do not care.

So similarly x1 is x, xx is also x, xz is also x. So, 0, z0 is 0, z1 is x as we have discussed earlier like here we have z1 is x and then we have zx is also x, zz is also x. So, this is the logic operations of AND gate for all combinations of the inputs. Similarly, you can have for OR gate, the other gates also, AND, NOR and remaining gates.

So, now using these basic gates, how to write a Verilog code? So, I will discuss a Verilog code for a simple circuit. called AND-OR inverter 4 input circuit.

This is AND-OR inverter 4 input circuit. As we have discussed this Verilog has a twofold operation. Verilog can be used for Describing the hardware given a circuit, we can describe by using the keywords.

We can describe the circuit or we can test the designed circuit. First, I am going to explain with an example how This Verilog code can be used for describing a circuit. The circuit that I have taken is AY4 means this is something like we have 4 inputs, 2 inputs for this AND gate, 2 inputs for this AND gate A, B, C, D. Then we have R gate and inverter, I am going to club these two together so that this becomes an R.

Basically, we have AND gate, R gate, NOT gate, inverter, AY. These four represent four inputs. Output letters call as Y. So, I want to describe this instead of drawing this diagram, I want to describe by using Verilog code. So, how to write the Verilog code?

So whatever the code that you have to write, we have to write between the module and end module. So, the starting this one is module, you have to give some name. So, I am giving the name of the module as AOI4 itself.

After reading the program, the last keyword is end module. So in between this, so whatever the description that you have to write. So, AOI followed by here you have to specify the inputs and outputs of the circuit.

So, we have one output and four inputs. First you have to specify output Y. Then the inputs a, b, c, d, so after that we require a semicolon here. Then you would describe what are these values, output y semicolon, input you have a, b, c, d semicolon.

So, this instead of writing these three I mean keywords, this can be described in a single keyword also like module is same, the name is also you can write the same name ay4. So within this bracket, here itself you can write output y comma input y comma input y have to give some tab, here you have to give the gap between after this output or after this input, a comma b comma c comma d. So, this single keyword is equivalent to these three.

So, you can write anyway. So, I am using this notation only. So, this definition of the input and output ports also you can give here itself.

Now, coming for this one. So, we have four input ports. This will be connected to the input port and this will be connected to the output port. In between if want to interconnect these gates, We require some wires. This is similar to the physical connection that you are going to give in a digital laboratory.

So, I want to connect the output of this AND gate to the input of this NOR gate. So, I require a wire, I will call this one as W1. Similarly, here also I require another wire W2.

So, you have to define this wire. Wires are basically easy to connect. the gates in the design, wire w1 comma w2 semicolon. Now, I can give some name for this AND gates and OR gates.

So, this I will call as A1, this I will call as A2, this I will call as N2. You can directly give this as an OR or you can give OR and NOT also, this is up to you. So, I am writing this primitive of the undecati as I have discussed in the earlier slide is and lowercase and.

And in the parentheses, you have to first write the output, which is w1 and you have to give the name because there are two AND gates to distinguish between these two, you can write a name. So, I am defining this AND gate as a1, for a1 what is the output w1 comma, the inputs are a comma b. Similarly, there is second AND gate a2, a1, a2, a1, a1, a1, Output is w2, the inputs are c and d.

Now the final output y will be the output of the NOR gate. So you can write directly NOR whose output is y, the inputs are w1 and w2. This w1, w2 you can write in any order. So, that is all. This is the description of this given circuit which is called as and R and inverter circuit.

So, you can also write this NAR as otherwise, this you can write using two, I mean, keywords. One is you can use R with the, so you have to define one more wire here. If you want to write this NAR as the inputs are w1, w2 and this is y, this is equivalent to R followed by you can define another w3 in that case you have to define here another w3.

gate, this is finally is y. So R, so you have tried here w3 in that case, output is w3, w1, w2 semicolon not y, w3. So this is how if you write this program, this will give you the description of the given circuit.

So, this is I mean Verilog is having twofold uses. One is it will describe the circuit. So we can test the designed circuit.

So, you have some design. So, normally how to test the design? Normally, you will connect using the ICs and I will test the functionality.

So, whereas using Verilog code, you can test the functionality of the design by writing the Verilog code. So, I will consider another example of how to I mean test the design. So, for that I have to first discuss how to design the digital circuit. We know that digital circuits can be broadly classified as. combinational circuits and sequential circuits.

So, combinational circuit is a logic circuit where the output at any time depends upon only the present input without regard to the previous outputs. Whereas, in case of sequential logic circuits, the output not only depends upon the present input, but also on the previous outputs. So, you need some memory in case of sequential to remember the previous output.

So, this requires some memory and there will be some feedback connection from output to input. So, first I will discuss the design of combinational circuits and the corresponding Verilog codes. CKT is the symbol for the abbreviation of circuit. So, there are certain rules for design of combinational circuits. So, step 1 for the design of the combinational circuit is, so you have to define the problem.

From the specifications, determine, so you will be given the specifications, determine the number of inputs available and the number of outputs required. Then step 2 is assign letter symbols to all the inputs and outputs. Third step is draw the truth table which describes the relation between the input and output.

Then next step is write the Boolean expressions for all the outputs. outputs and simplify by using KMAP and next step is this is the last step draw the logic diagram. Once the logic diagram is obtained to check the functionality normally we will connect.

using the ICs. For a simple circuits which contains less number of gates, you can test manually. But in case of VLSI circuits where millions of the gates are there, then you have to go for the computer aided designs. So, here in order to test this logic diagram that we have obtained from the design, so you can write a Verilog code and you can run the simulation. You can give the different combinations of the inputs and you can check the outputs.

So, in order to explain this design rules or design steps, I will take an example of a 3 bit squarer. So, the problem statement is given, how to obtain the logic diagram which I mean squares the 3-bit input value. So, the first step is how to determine the number of inputs available, is already given that 3-bit.

So, number of inputs are 3. Then how to find out the number of outputs required? So, basically this circuit has to square the input number, you have 3 bits, say you have a2, a1, a0 is the 3 bit number, this is 3 bit square, so how many outputs are required? How to find out this? So, what is the maximum 3-bit number?

So, the maximum 3-bit number is all the a2, a1, a0 should be 1, 1, 1. This is in binary, this is 7 in decimal. If I square 7, then I get what is the value? 49 is the decimal value. Sorry, this is decimal 1, 0 stands for the decimal base.

So, what is the binary equivalent of 49? So, so many bits are required. at the output because you have to accommodate the maximum possible value also.

So, 49 if you convert into binary 24 0 1, 2 12 0 0, 2 6 0 0, 2 3 0 0, 2 1 0 0 1. 2 0s 1. Until the quotient is 0, you have to stop here and you have to read this value from bottom to top. So, what is that value? Is 1 1 0 0 1. If you want to verify, you can verify also the weight of this one is 1 in decimal, this is 2, this is 4 parts of 2, this is 8, this is 16, this is 32. So, basically you are adding 32 because 1, 32 plus 16 which is 32. is equal to 48 plus 1 is 49. So, this in binary form is 1 1 0 0 0 1 in binary. So, we require 6 outputs.

So, 6 outputs are required. So, starting with y 5, y 4, y 3, y 2, y 1, y 0. I am assigning the letter symbols. I am finding this one. The second one is I am assigning the letter symbols. I am assuming that a2, a1, a0 is the… This is second step also I have combined this.

Step 1 and step 2 I have combined together. So, I have sent the letter symbols for the inputs as a2, a1, a0 and outputs as wi-fi to y0. Wi-fi is the MSB, y0 is the LSB. Wi-fi I have called as MSB. You have to clearly define this, y0 is LSB.

MSB stands for most significant bit, LSB stands for least significant bit. The third step is you have to draw the truth table. For all the combinations, how many combinations are there because inputs are 3, a2, a1, a0.

So, we have 8 combinations. Outputs are 6. So, y5, y4, y3, y2, y1, y0. So you take all the 8 combinations 0 0 0, so you found you can write the decimal value also here, decimal input value, decimal output value so that we can easily understand this problem, decimal output, decimal input.

So, 0 means 0, 0 square, what is the decimal equivalent value? 0 only. So, what is 6 bit equivalent of 0? All 0s. Decimal 1, if the input is decimal 1, the representation in input binary is 0 0 1. 1 square is decimal is also 1. How to represent 1 using 6 bits?

0 0 0, 0 0, 1. If the input is 2, the binary representation of 2 is 0 1 0. So, the decimal square of this one is 4. So, how to represent 4? 0 0 0, 1 0 0. If the decimal value is 3, the binary representation is 0 1 1, 3 square is 9, how to represent 9? 0 0 1 0 0 1, these are basically the weights you can add.

This weight is 1 2 4 8 16 32. So to get 9, you have to add 8 plus 1, 4 1 0 0. So, this is basically 16, 16 is directly there. So, 0 1 0 0 0 0, 5 1 0 1, 5 square is 25, to get the 25 it is 16 plus 8 is 24 plus 1. So, 0 1 1 0 0 1, 6 is 1 1 0, 5 1 1 0 1, 6 square is 36, 32 plus 4, so 1 0 0 1 0 0, 7 1 1 1, 7 is 49, we have obtained this. 32 plus 16 plus 1. So, you see the truth table.

So, which will describe the given problem. For all the combinations of the inputs, it will give the output square value. So, what is next step?

Step 4 is You have to obtain the Boolean expressions for the all the outputs and you have to simplify by using KMAP. You can see that one, even if you simplify also you will get same thing, y naught is nothing but this is 0 1 0 1 0 1 0 1, a0 also 0 1 0 1 0 1 0 1. So simply y0 is equal to, this is by observation, you can do it by using KMAP also you will get same thing, this is by observation. And y1 is always 0, y1 is always 0 and y2 is what are the minterms? y2 is sigma m.

So, wherever Boolean expression you have 1, this 1 is correspond to this minterm 2, 2, this minterm is 6. You can use the K map. Basically, the inputs are, a2, a1 this is up to you can write in any way. I am writing a2, a1, a2 is MSB, a0 is LSB or you can write a2, a1 here and a0 here. So, in any case you will get the same final expression. So, we know that we are going to use gray code to number the rows and columns 0, 0, 0, 1, if it is binary 1, 0, 1, 1, if it is a gray 1, 1, 1, 0. So, this box number is 2, 2 means 0 1 0, 0 1 0 is this is 2 and 6 is 1 1 0, 1 1 0 is this, this is 2 box combination.

So, therefore, y 2 is equal to. So, here the variable that is changing will get cancelled, a2 is 0 here, a2 is 1 here, so a2 will get cancelled, a1 is constant at 1, so you have to take without complement, whereas here a0 is 0, so this is a0 bar a1. Similarly, you can get y3 as sigma m is the min term is 3, 5. So, this is a2, a1, a0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 3, 5, 0, 1, 1 is 3, 5 is 1, 0, 1. So, you see nothing but just there is no mean combination at all this is single box combination, this is single box combination. So, you will have y3 is equal to this expression is a2 bar a1 a0 plus this one is a2 a1 bar a0. So, a0 is common you can write this one as this is y3.

This is equal to A naught is common then it is exclusive or between A2 and A1. So, A naught times A2 exclusive or with A1, y4 sigma m mean times are 4, 5, 7. So, 0 0 0 1 1 1 1 0 0 1 a 2 a bar a naught. So, 4 5 7 1 0 0 5 is 1 1 1 0 1 7 is 1 1 1. So, these are two box combination, this is another two box combination.

So, therefore, y 4 is this expression is a naught will changes. So, this is a 2 a 1 bar. and this one is a naught and here a2. So, a2 is common and similarly y5 is equal to sigma m67.

So, if you simplify this, you will get 00011110 a2 a1 a naught. 6 7 1 1 0 1 1 1. This is a two box combination. This is simply Wi-Fi is A2 A1.

So, these are the final expression, then we have to draw the Boolean, the logic diagram. So, I will draw here the expressions for y0, y1, y0 is a0, y1 is 0, y2 is, y2 we have got this y2 as a0 bar a1, y3 is A2 exclusive or A1, y4 is A2 into A1 bar plus A naught, A2 into A1 bar A naught and y phi is A2 A1 right. So, the last step is you have to draw the logic diagram.

So, you can draw this logic diagram using gates. Now, synatom in write the Verilog code correspond to this one, module Using this Boolean expression directly I am writing the Verilog code or otherwise you can draw the logic diagram so that it will be easier. So this will be y naught is a naught, you have 3 inputs a naught, a1, a2 and the corresponding complements.

You see how you can draw the logic diagram easily. You have a naught and if I connect through the naught gate a naught bar. This is a1, if you connect the not gate between this, you will get a1 bar, this is a2, this is a2 bar, so you have a not gate. So to get this is a0 directly you have to connect this from the a0, this is your y0.

So y1 is basically ground, y2 is a0 bar a1, a0 bar line is this. A1 is this, this is y2, y3 is A0 into A2 exclusive or A1, A2 line is this, A1 line is this. This is exclusive R and this you have to end with a naught. This is your y3 and y4 is a2 into a1 bar plus a naught. a1 bar is this plus a naught is this R operation and you have to end with a2.

This is A2 and Wi-Fi A2 A1. This is the complete design of this one. If you want to verify this normally we will in manual mode we will connect the ICs correspond to all the logic gates and we will verify. Whereas in Verilog code, if you want to write Verilog code, module, I will give the name as square R, output is y0 so on up to y1, y2, y3, y4, y5 comma a2, a1, a0 semicolon output. y0 comma y1 comma y2 comma y3 comma y4 comma y5 semicolon input a2 comma a1 comma a naught semicolon.

Then how to get output y? y naught is same as a1, for that you can write buffer. buffer because buffer will give the same output is equal to input, buffer with output as y naught input as a naught and y 1 is 0, you can directly give assign y 1 is equal to 0. is 0 or we can give, if want to use a gate then you can use something like AND y1 inputs if you give any input like a2 comma a2 bar, if I give 0 say other input.

This is up to you can design in many ways, you can assign directly in case of behavioral modeling. I will discuss that in the coming classes, this is 0, a2 comma 0. Then y2 is nothing but, so y2 you want a0, first you obtain this a0 bar, a1 bar, a2 bar using three NOT gates, NOT, so you call this one output as a0 bar, a0, NOT. bar, sorry a1 bar a1, not a2 bar a2. Then y2 is AND, AND y2 comma inputs are a0 bar a1, a0 bar we have already obtained. And, y3 is, you have to first, we have to define the wire here, we have to define wire y1, w1.

So, xr, xr, output is w1, the inputs are a2 and a1. Then, we have to use end operation, end, output is y3, the inputs are w1 and then a0. Then y4, first you have to write R between A1 bar and A naught, this output you call as yw2, so w2 comma, the inputs are A1 bar comma A naught, then AND between output is y4, input is w2 comma, the other input is A2.

and Wi-Fi is AND between A2 and A1, output is Wi-Fi A2 comma A1 and module. This is the complete design using Verilog. So if you run this program and if you simulate this A0, A1, A2. a naught, this you can give 0 or 1, this you can give 0 or 1 using the simulation tools and you can observe these outputs y5 to y0, y5 to y0, it has to satisfy the truth table that I have written in the previous slide.

This is how you can check using this Verilog code. This is all about this first design. So, in the coming classes, we will discuss some more examples of the combinational circuits. Thank you.

Transcript for:Understanding Gate Level Modelling in Verilog

Transcript for:
Understanding Gate Level Modelling in Verilog