I²C Communication Protocol

Introduction

• Microcontrollers and Multiple Devices: Data and address lines from multiple devices occupy significant pins.
• Bus System: Common communication path for data transfer between integrated circuits.
• I²C Bus: Two-wire, bi-directional serial bus for communication.

Overview

• Full Form: Inter-Integrated Circuit.
• First Introduced: By Philips Semiconductor in 1982.
• Widely Used For: Attaching low-speed peripheral ICS to processors and microcontrollers in short distances.
• Features: Multi-slave and multi-master communication.
• Components:
  • SDA (Serial Data Line)
  • SCL (Serial Clock Line)

Historical Milestones

• 1981: Patent filed by U.S Philips Corporation.
• 1982: Original 100 kbps I²C system created.
• 1992: Standardized version with 400 kbps fast mode and a 10-bit addressing mode.
• 1998: I²C bus became a world standard.
• 2000: Version 2 clarified.
• 2007: 1 Mbps fast mode plus (version 3).
• 2012: 5 Mbps ultra-fast mode (version 4).
• 2014: Revised versions 5 and 6.
• 2021: Version 7 released (changed terms: controller/target instead of master/slave).

Working Principle

• Devices: Masters and slaves.
  • Master Device: Controls communication and generates clock signal.
  • Slave Devices: Connected to bus and respond to master commands.
• Transmission: Series of bytes over SDA line.
• Clock Synchronization: Master generates clock pulses on SCL line.

Steps in I²C Communication Protocol

1. Master Issues Start Condition: Inform slaves to listen to the SDA line.
2. Master Sends Address: Compared with slave device addresses.

• Matched Address: Device is selected.
• Unmatched Address: Devices are disconnected.

3. Slave Responds with Acknowledgment: Communication established.
4. Data Transmission: Master and slave send/receive data.
5. 8-bit Data Transmission: Master sends 8-bit data, receiver sends 1-bit acknowledgment.

Data Transfer Format

• Five Segments:
  1. Start and stop bits
  2. Address bits
  3. Read or write bit
  4. Acknowledge bit
  5. Data frames

Start and Stop Bits

• Start Condition: High to low transition on SDA while SCL is high.
• Stop Condition: Low to high transition on SDA while SCL is high.

Address Bits

• Frame after Start Bit: Transmit slave's address.
• Address Match: Slave transmits low voltage acknowledgment.
• No Match: Slave remains idle, SDA line stays high.

Read or Write Bit

• Indicates Operation:
  • 1: Master transmitting data.
  • 0: Master receiving data.

Acknowledge Bit

• Acknowledgment: Verifies successful transmission of data/address.

Data Frame

• Master Sends 8-bit Data: Slave receives and sends acknowledgment bit.

Transmission Modes

• Standard Mode: 100 kHz, 100 kbps.
• Fast Mode: 400 kHz, 400 kbps.
• High-Speed Mode: 1 MHz, 3.5 Mbps.
• Ultra-Fast Mode: 5 Mbps (unidirectional).

Multi-Master Capability

• Arbitration: Ensures only one master controls the bus at a time.
• Physical Bus Setup: Wired AND configuration to detect bus occupancy.

Synchronization and Arbitration

• Multiple Masters: Monitor SDA and SCL for bus status.
• Conflict Detection: Uses bus signals to avoid data collision.

Clock Stretching

• Purpose: Allows a slave to stretch the clock when it needs more time.
• Master: Required to read back the clock to determine bus state.
• Mechanism: Slave holds SCL line low until ready.

Advantages and Disadvantages

Advantages

• Efficient: Multiple masters and slaves on two wires.
• Acknowledgment: Confirms successful data transmission.

Disadvantages

• Half-Duplex: Communication interface.
• Complexity: Increases with the number of devices.

Applications

• System Management: For PCs via SM bus control.
• Communication: Between multiple microcontrollers.
• User Interface: Monitors for backlight, color balance adjustments.
• Display Control: Small LCD or OLED displays.

Conclusion

• Commonly used protocol with efficient and flexible characteristics for a wide range of applications.

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