when we are using multiple devices with a microcontroller the data and address lines of every single device will occupy significant pins in the process of communication so transmitting and receiving information between two or more devices require a common communication path called a bus system for the purpose of transferring data between integrated circuits there is a bi-directional two-wired Serial bus called the I Square C bus in this video we are going to explain the I Square C communication protocol in detail so stay tuned and welcome to SD robotics [Music] [Applause] the I Square C stands for inter-integrated circuit it was first introduced by Philips semiconductors in 1982. it is widely used for attaching lower speed peripheral ICS to processors and microcontrollers in short distance or inter board communication this is a multi-slave and multi-master communication protocol that gives the flexibility of connecting multiple IC at a single instance of time to a single bus I Square C is a communication protocol that allows devices to exchange data with microcontrollers or computers it is a two-wire Serial protocol that uses one wire for data transmission called SDA or serial data line and another for clock synchronization called scl or serial clock line i2c is commonly used in microcontrollers and computer systems to communicate with sensors eproms and other peripherals it is a relatively simple protocol that can be used to connect a large number of devices to a single microcontroller or computer making it a popular choice for a wide range of applications history of I Square C protocol before going into the I Square C working principle let's have a look at its history in 1981 a patent was filed on November 2nd by U.S Phillips Corporation in 1982 the original 100 kbps I Square C system was created as a simple internal bus system for building control Electronics with various Phillips chips in 1992 400 kbps fast mode and a 10-bit addressing mode increased capacity to 1008 nodes this was the first standardized version in 1998 the I Square C bus has become a world standard that is now implemented in over 1000 different I cease and license to more than 50 companies in 2000 version 2 has been clarified without significant functional changes in 2007 one megabit per second fast mode plus was introduced in version 3. in 2012 five megabits per second Ultra fast mode for new USDA and uscl lines was introduced in version 4. in 2014 revised versions 5 and 6 were released with some minor Corrections in 2021 version 7 was released with change terms controller Target instead of Master Slave to align with a 3C bus specifications we will try to understand how I Square C protocol works the I Square C communication protocol Works through SDA or serial data and scl or serial clock initially both the SDA and scl lines are pulled High using a pull-up resistor in this protocol there are two types of devices Masters and slaves the master device controls the communication and generates the clock signal that synchronizes the data transfer the slave devices are connected to the bus and respond to the commands of the master the master can send or receive data to or from the slave by transmitting a series of bytes over the SDA line the scl line is used to synchronize the data transfer the master generates clock pulses on the scl line and the slave devices latch the data on the falling edge of the clock pulse now we will know the steps involved in I Square C communication protocol in the I Square C protocol the number of slave devices is connected to the master device with the help of the I Square C bus wherein each slave consists of a unique address to communicate it the following steps are used to communicate the master device to the slave Step 1 first the master device issues a start condition to inform all the slave devices so that they listen to the serial data line Step 2 the master device sends the address of the target slave device which is compared with all the slave devices addresses as connected to the scl and sdl lines if anyone's address matches that device is selected and the remaining devices are disconnected from the scl and sdl lines step 3 the slave device with a matched address responds with an acknowledgment to the master thereafter communication is established between both the master and slave devices on the data bus step 4 both the master and slave receive and transmit the data depending on whether the communication is read or write step 5 then the master can transmit 8-bit of data to the receiver which replies with a one bit acknowledgment let's have a look at the data transfer format in the I Square C protocol the data transfer format of the I Square C protocol is divided into five segments start and stop bits address read or write bit acknowledge bit and data frames start and stop bits all i2c transactions begin with a start and are terminated by a stop for the start condition high to low transition occurs on the SDA line while scl is high for the Stop condition a low to high transition occurs on the SDA line while scl is high address this is the immediate frame after the start bit the master bit transfers the slave's address with which it has to communicate then the slave bit Compares its own address with the address of the slave that was sent by the master when both addresses match it transmits a low voltage acknowledge signal to the master signal whereas when both the addresses do not match the slave remains idle and the serial data line stays at High read or write bit when the read or write indicates one then the master is transmitting data to the slave whereas when read or write indicates zero then the master is receiving data from the slave signal acknowledge bit the acknowledge or no acknowledge bit is the subsequent bit of every frame in a message when data or address was successfully transmitted then the ack signal gets back to the sender from the receiver device data frame when the ack bit is detected by the master from the slave it indicates that the First Data frame can be transferred this data frame is of 8-bit length after the data frame ack or nak bit detects the successful transmission of the frame once the transmission was successful then the next data frame will be ready to transmit there are four types of transmission modes in the I Square seat protocol standard mode fast mode high speed mode and Ultra fast mode in standard mode the scl frequency is limited to 100 kilohertz and the data transfer rate is typically around 100 kbps this mode is suitable for low speed applications and long distance communication in fast mode the scl frequency is increased to 400 kilohertz and the data transfer rate is typically around 400 kbps this mode is suitable for high-speed applications and short distance communication there is a high speed mode that allows for scl frequencies up to 1 megahertz and data transfer rates of up to 3.5 megabits per second there is also an ultra fast mode with data transfer rates of up to 5 megabits per second but in this mode data transfer is only unidirectional it is important to note that not all i2c devices support fast mode or high speed mode and the maximum scl frequency and data transfer rate will depend on the specific device and the capabilities of the bus so far we have seen the operation of the bus from the master's point of view and using only one Master on the bus the I Square C bus was originally developed as a multi-master bus this means more than one Master can attempt to control the bus simultaneously without corrupting the message in such a case each device needs to be able to cooperate with the fact that another device is currently talking and the bus is therefore busy arbitration is the procedure to ensure that if more than one Master simultaneously tries to control the bus only one is allowed to do so arbitration several I Square C multi-masters can be connected to the same I Square C bus and operate concurrently by constantly monitoring SDA and SEL for start and stop conditions they can determine whether the bus is currently idle or not if the bus is busy Masters delay pending i2c transfers until a stop condition indicates that the bus is free again let's assume one of the Masters missed the start condition and still thinks the bus is Idle or it just came out of reset and wants to start talking on the bus or two masters begin transmission at the same time which could very well happen in a real life scenario so that is a conflict how does a master know if another Master is transmitting data on the bus fortunately the physical bus setup helps us out since the bus structure is a wired and which means if one device pulls a line low it stays low you can test if the bus is Idle or occupied when a master changes the state of a line to high it must always check that the line really has gone to high if it stays low then this is an indication that the bus is occupied and some other device is pulling the line low therefore the general rule of thumb is if a master can't get a certain line to go high it lost arbitration and needs to back off and wait until a stop condition is seen before making another attempt to start transmitting the procedure to synchronize the clock signals of two or more Master devices is called synchronization similar to the SDA line scl line is also logic high due to the pull-up resistor and it also acts as a weird end to understand the synchronization process let's look at the figure this figure has two clock signals driven by two masters Master one pulls the clock low before Master 2 as a result scl becomes low after a few moments Master II pulls the clock low and now both are in the same state now Master One released the clock but as the scl is still held by Master 2 Master 1 has to wait until Master 2 also releases the SEO when both the Masters release the clock line scl becomes High so the low period of the resultant clock is determined by the master with the longest low period and the high period of the resultant clock is determined by the master with the shortest High period clock stretching in an i Square C communication the master device determines the clock speed unlike the I Square C bus provides an explicit clock signal which relieves master and slave from synchronizing exactly to a predefined baud rate however there are situations where an i Square C slave is not able to cooperate with the clock speed given by the master and needs to slow down a little this is done by a mechanism referred to as clock stretching an i-square seat slave is allowed to hold down the clock if it needs to reduce the bus speed the master on the other hand is required to read back the clock signal after releasing it to the high State and it forces the master into a weight state when the slave is ready for the next bite it releases the scl line and the master then resumes the transaction the I Square C communication protocol has various advantages like it is efficient because it allows multiple Masters and multiple slave communication it allows communication using two wires only it uses an acknowledgment that that confirms every data frame is successfully transmitted this protocol has a few disadvantages like it is a half duplex communication interface and its complexity with increasing numbers of devices the I Square C is appropriate for peripherals where Simplicity and low manufacturing costs are more important than speed common applications of the I Square C bus r system management for PC systems via SM bus to control a network of devices or sensors chips with just two general purpose I O pins and the software of a microcontroller communication with multiple microcontrollers changing backlight contrast Hue color balance settings Etc and monitors transmitting and controlling user-directed actions controlling small LCD or OLED displays Etc [Music] you can learn something new from this video if you like the video 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