Digital PLL Lecture Notes
Overview
- Previous Session: Simplified block diagram of a digital PLL
- This Session: Detailed function of digital PLL components, with a focus on TDC (Time to Digital Converter)
Simplified Block Diagram of Digital PLL
- Components:
- TDC (Time to Digital Converter): Converts phase error to digital bits
- Digital Loop Filter:
- Proportional path gain (Kp)
- Integral path gain (Ki)
- Accumulator (z⁻¹ models the delay)
- Digital to Analog Converter (DAC): Converts digital control word to control voltage
- Oscillator controlled by voltage from DAC
- Feedback divider for frequency multiplication
- Signals:
- Reference frequency (Input)
- Output frequency (Controlled by V-control)
- Symbols:
- d<sub>tdc</sub> (Output of TDC)
- d<sub>p</sub> (Output of proportional path)
- d<sub>i</sub> (Output of integral path)
- d<sub>f</sub> (Combined digital control word)
Time to Digital Converter (TDC)
- TDC Function: Measures phase error between reference (R) and feedback (V) clocks, converting it into a digital word (d<sub>tdc</sub>)
- Digital Word: x-bit representation of phase error
- Error Measurement:
- TDC Range: Typically counts phase error from -T<sub>ref</sub> to +T<sub>ref</sub> (2T<sub>ref</sub> total)
- Digitizing Phase Error: Phase error (∆t) converted to binary equivalent using TDC resolution (∆t<sub>LSB</sub>)
Key Equations and Concepts
- Analog to Digital Conversion: A<sub>error</sub> = (Voltage/Reference Voltage)
- Digital Output Calculation: For phase error ∆t
- ∆t digitized to control word d<sub>tdc</sub>
- ∆t<sub>LSB</sub> (Resolution):
- ∆t<sub>LSB</sub> = 2T<sub>ref</sub>/2ⁿ
- d<sub>tdc</sub> Calculation: d<sub>tdc</sub> = (∆t/∆t<sub>LSB</sub>)
- Gain: K<sub>tdc</sub> = (2ⁿ/(4π)) × φ<sub>error</sub>
Example
- N-bit TDC with resolution ∆t<sub>LSB</sub> for 10-bit word:
- N = 10, ∆t<sub>LSB</sub> = (2T<sub>ref</sub>) / 2¹⁰
- Digital Equivalent Calculation:
- For phase error of 496: d<sub>tdc</sub> ≈ 0100000000 (binary), 496 (decimal)
- Phase error φ<sub>error</sub> = (4π × 496) / 1024
Implementation of TDC
- Simple Delay Line Implementation:
- Delay line with 2ⁿ delay cells (Each cell delays signal by ∆t<sub>LSB</sub>)
- Sampled outputs by clocked registers
- Registers store values at rising edge of reference clock
- Sum of register values gives phase error
- Delay Line Setup:
- Ensure delay line = 2T<sub>ref</sub> for accurate error measurement
- Each cell delay = 2T<sub>ref</sub>/2ⁿ = ∆t<sub>LSB</sub>
- Resolution and Range:
- Range of TDC: 2T (or T)
- Number of delay cells ∝ Reference Clock Period
- Quantization Noise:
- Limited by ±(∆t<sub>LSB</sub>/2)
- Actual phase error: φ<sub>error</sub> = (phase error + quantization noise)
TDC Small Signal Model
- Concept: Measure φ<sub>error</sub>, digitize via TDC to output d<sub>tdc</sub>
- Gain of TDC: K<sub>tdc</sub> = (2ⁿ/4π)
- Model:
- φ<sub>error</sub> = φ<sub>ref</sub> - φ<sub>fb</sub>
- d<sub>tdc</sub> = [φ<sub>error</sub> × K<sub>tdc</sub>] + quantization noise (q<sub>tdc</sub>)
Conclusion
- Key Takeaways:
- TDC converts phase error between reference and feedback to digital control word
- Accurate measurement hinges on precise delays (∆t<sub>LSB</sub>) and number of delay cells
- Quantization noise affects accuracy but is limited to ±(∆t<sub>LSB</sub>/2)
- Small signal model includes both gain and quantization noise
Note: Multiple TDC implementations exist; refer to literature for more complex designs.