[Music] hello everyone welcome to this session in the previous session we arrived at the simplified block diagram of a digital pll okay so let me just draw that so in the digital pll we have a tdc which converts the phase error to digital bits you will look at it how it works and the output of the tdc goes to a digital loop filter which has the gain of proportional path kp and the integral path gain ki and here you feed it to an accumulator i will write that with its small signal diagram you can say or the block diagram so you have an accumulator like this where this is z inverse this models the delay and this is the accumulated value the output of the proportional path and the digital path they add together to give you the final control word which is going to control your oscillator and then you have digital to analog converter which converts the an digital world to the control voltage this controls the oscillator okay and then you can have the feedback divider as required for the frequency multiplication this is your reference frequency and this is your output frequency okay the output of the tdc i call this as d tdc the output of the proportional path this is dp output of the integral path is d i when you combine them you get the digital control word df and df gets converted to the voltage v control and that is the output frequency okay so your output of the oscillator is still a voltage waveform as it used to be we cannot change that similarly the input of the tdc which is the reference clock and the tdc clock they are also voltage waveforms so here if you look at it by the way i will just put everything here in one single block and call it as it is normally called a digital loop filter okay so here tdc is time to digital converter and how it works let us look at it so the block tdc has two inputs the reference and the feedback and the output is a control word or a digital word which is dtdc when we say it is a digital word it can it is like a x bit word so if we have these two signals r and v like this r is the reference signal which is like a reference coming from crystal of or some other source you have a reference clock v is the feedback clock it can be the same frequency of course different frequency also if it is there and what we are going to do is we are going to calculate this error between these two rising edges as was done in the case of pft so if you remember in the case of pft you had up minus down and depending on your up minus down you get this error whether it is like this or in other case up minus town can be negative also that was a case with pft now we do not have the pft what we want to do is we want to use this delta t time and convert the delta t time into its digital equivalent that's what is tdc is doing so here you have a reference clock period which is capital t okay so all so the uh clock which acts as a reference in the measurement of time is your reference clock itself okay so this delta t error is now digitized right in some digital world so first thing which i will tell here is that in the case of pfd if you remember you measured the phase error t and it was like minus 2 pi to 2 pi it was a linear transfer function okay so similarly here if this in one case you are seeing the error is this in the other case i can have the rising edge of the clock maybe coming like this so late just an example so this is the difference between another the rising edge is delayed and it is delayed by delta t which is closer to you can say one reference period okay similarly you can have delta t where the rising edge on r comes after the rising edge on v and that also period can range from small delta to l to a large value of delta t so here the range of the tdc which we the range of phase error measurement which are normally used range of phase error of measured by tdc is typically two reference period okay so you can say uh plus t ref minus t ref 2 plus t left it gives you plus minus 2 pi that's the maximum which you can have or which you will use in general now this delta t is digitized to the control word dtdc okay this delta t timing so in order to digitize this delta t timing you need a reference or some resolution so this delta t i need to digitize so when when you have a voltage for example delta v and you want to convert it into a discrete value d what you need is a reference voltage for or whatever is your comparator threshold okay the digital this is like analog to digital conversion analog to digital conversion requires analog traditional conversion requires threshold voltages for comparators for comparator okay similarly delta t to tdc dt dc requires your resolution delta t you can say lsb or delta t threshold delta t resolution or delta t lsp to convert from ah or you can say this delta t u t d c requires some kind of delta t resolution okay delta t l s p which what it means is the following if the phase error is something like this with just an example this is r and let us say this is v and this separation between r and v has multiple or you can say multiple slots each slot is like each slot is delta t lsb if such is the case then you can count how many slots do we have between these two rising edges one two three four five six seven eight nine so nine completes lost and the tenth slot is half so depending on how you are giving the compared value you can say the separation between these two rising edges is or this particular value this delta t is approximately 9 times delta t lsb so this is something which you need based on this you can convert your this 9 to a digital world so if i have nine bit nine as the delta t lsb my dtdc i can very well write for above case delta t is actually when i found the separation between these two rising edges it gave me this is approximately equal to 9 times delta t lsb so if there is some information about delta t lsb then taking that into account i can say my dtdc is nothing but here let us say i am having a 5 bit word so i will write 5 dash b this just nomenclature we normally use and this is 9 here so 0 1 0 0 1 so this is this digital word the placement values are 2 power 0 2 power 1 to power 2 to ah to power 3. so you have equivalent decimal equivalent is 9. so this is how you are going to convert so if you look at it what we need from the this tdc block is the information about what is the delta t lsb and the range which we are going to measure is with the tdc normally max that will be minus 1 reference period 2 plus 1 reference period like the one which we had here ok minus 1 reference period is minus 2 pi plus 1 reference period is plus 2 pi so this range so range of the tdc is 2t and what you have here is the delta t lsb information which you need so if n bit tdc okay and n bit tdc with range 2 times t implies that your delta t or the resolution delta t lsb is equal to your 2 t range divided by n bit t d c so you know n bit t d c how much is the maximum value so you can say this is approximately 2 power n values you will have so this is your delta t lsb okay and the digital word which you are going to get the digital word will be having an equivalent binary equivalent binary value okay so what i am going to get how i am going to write this performance of the tdc so given phase error okay now you have to because you are doing it digitally so you have to specify whether you are going to have a positive or negative okay the phase error so here let us say we take that into account later the whole 2t range which is from minus t to plus t is given by n bits okay so given phase error phi error as 2 pi times delta t by t this phase error is converted by tdc to you can say the digital equivalent of so you can always write delta t as t over 2 pi times phase error ok so the decimal equivalent of this value is delta t divided by delta t lsb which is t divided by respect to t divided by 2 pi of phase error divided by l s p which is 2 t divided by 2 power n which in turn is equal to 2 power n by 4 pi times phase error okay so here the thing is that i have taken the range 0 to 2 t you can take the range minus t 2 to a t also the only thing is you have to then take into account the positive and the negative we can take that into account in digital case also so this tdc is if you have a phase error phi r this phase error phi r is converted to its digital equivalent as you see here by the way this is the bind this is decimal equivalent okay whatever value you get here the the phase error is actually that value into delta t lsb but this is what you are going to get from the tdc this is decimal equivalent and this you do decimal to binary you do decimal to binary so that you get d t d c okay so if i write d t d c as though it is a binary value it you can say this is like n bit whatever number you have this binary value is 2 power n divided by 4 pi times phi error so if your phase error is 4 pi 4 pi is your 2t okay 2 times the time period your decimal equivalent is 2 power n your phase error is 0 decimal equivalent is 0 equal to 0. so this is effectively the gain of n bit tdc in general okay so when you get when you use the tdc here in this pll you have a phase error okay and this is an n bit tdc and the n bit expands the range minus t to plus t in that case whatever the dtdc value you are getting i told that in here i have been using this dashed line here this dashed line just means that there are n there are multiple signals so if i want to write this as an n bit tdc i will say it and here so this n bit tdc gives you this dtdc so if you just look at independently the value of n bit tdc and n with tdc equal to some value in terms of 1000 or other things so if n is example right if n is 10 bit for example and it's 10 in that case and my dtdc value happens to be something as let us say it is 496 okay this is the numerical value the decimal value in binary case you can say this 10 bit dc the decimal value is equal to this is going to be 0 then you have 256 so 10 bits will be there you will have 256 you are going to have 128 then you will have 64 all right and you will also have 32 and rest all are going to be 0 16 8 0 4 8 4 2 1. so what you see here is that the digital equivalent is going to be this okay whereas the decimal equivalent is this here 496 doesn't mean the error is 496 times the reference period well this 496 means phase error is actually phase error is so phase error is 4 pi divided by 2 power n times d t dc this is what we have so it is 4 pi divided by 2 power 10 times 496 this is the phase error value of c so 4 pi times 496 by 1 0 to 4. this is the phase error which you see so what what is the meaning of the dtdc output that is clear by now that it measures the timing difference between the reference and the feedback clock what you need is delta t lsb somehow you have to uh get it okay and once you get that you have to create this delta tlsp in a similar way as you as you generate the comparator threshold once you get that dtdc this is what it will mean now a typical implementation we will not go that much detail but a typical implementation of tdc is as follows tdc there are multiple ways in which you can implement okay tdc so one way is that let us say i have delay line so okay this is the delay line which consists of two power and delay cells okay so this i will node may name this node as q one q2 q3 and so on and it goes up to q in q to power n so all these are delay cells these outputs okay these outputs are fed to registers so if i write it like this let me just make it a one single and then copy paste okay so these are fed as inputs and you have a clock here okay and this is your output q so this is your register by the way so you have these registers normally you what you will see is just one single line saying that these are resistors okay they are not connecting by the just disconnect them in a moment okay and similarly you have on all the cases which you have so these are registers which are clocked so i am having a clock which connects all of these registers so let me just connect this so a clock is there which connects to all of these blocks finally it comes here okay so this i am going to call as let us let me call this as r1 r2 r3 r to power n okay and this clock what you are seeing here is another signal which is your reference signal and this is your feedback signal now if i make sure that the delay from here to here okay delay of combined delay of [Music] 2 power n delay cells is 2 reference period this is may sure independently okay then delay of each td delay of each cell is nothing but 2 t divided by 2 power n which acts like delta t lsb in our case okay so now just think about it let us say when you get you are having the reference clock coming like this this is your reference clock and your feedback clock is coming somewhere here this is a feedback log so you start looking you feed these two signals to the feed these two signals to your circuit ever with respect to time okay so when and let us say all the signals start at time instant t equal to 0. before that all the signals were actually 0. so in that particular case if i look at r1 r2 r3 and so on i am looking all these values so i will look at r1 r2 r3 and so on you can say r into 2 power n so as you see from here when i just so these are the registers which sample the value at the rising edge so when the first rising edge on r comes what you sample is 0 0 0 and 0 all of them are 0 then after some time you see a rising edge on v coming after a certain delay okay if it is after a certain delay that you get rising edge on v then that rising edge on v is going to propagate through these delay cells after delay so if i look at here my q1 okay q1 will actually become one this i am this is not r1 signal but i am just plotting this is your q1 after the delay right qt q2 signal will actually become 1 after another delta t lsp delay similarly q3 signal will become one after so this is q2 this is q3 it will become after some delay right since the range of this tdc this delay line 2 is 2t right so the delay of you will not till the time you get the rising edge here you will not be able to get q in 2 power ns 1 okay so then what happens is that few of them will still be 0 and others will become 1. so when you get the next rising edge at next rising edge r1 will be sampled as 1 r2 will be sampled as 1 r 3 will be sampled as 1 and similarly r4 and other values will be sampled as 1 and the some other values will be sampled as 0. okay so you can think about it that the number of flip flops which will register value 1 at the next rising edge okay so number of flip flops which will register value n at the next rising edge those number of flip flops can you can say if this whole delay it will be easy for you to understand like this if this whole delay is 2 times t depending on how you choose you can also choose a range of for t okay this is just one example if you choose a range of 2t then you can say that 2t minus whatever this phase error is right just an example this if this the delay of the elements till here is delta t then only the resistors which are coming before this they will register 1 other values will register as 0. so when you sum up all these register values right when you sum up all these register values you will find that you can easily calculate this one delay so range is 2t you have this delta t so whatever value you are going to get at that point right you can actually uh find what is the decimal equivalent okay so what we need is that whatever these register values you get these register values are saved and these register values are summed up to give you a representation for this delta t error okay so what you see here is that we need such delay cells okay we need the resistors to get the to latch these values right there is other way to detect the so this is one simple method right the important part here is that you need to get this delta t somehow this has to be tuned your lsp size is what you require and this has to extend over the whole reference clock period right so this is a simple implementation there are multiple ways in which you can implement the tdcs ok you can always refer to the literature for that so if i just want to conclude the tdc part the thing is that you require delay cells with delay tuned to delta t lsp this is important because if the delay of these elements which you are seeing here is not delta t lsb is something else or you do not know then you cannot comment on what the phase error you have so somehow you have to make sure that the delay is fixed or within the margin of error what you can tolerate okay and the number of delay cells number of delay cells which you require is proportional to your reference clock period sometimes you make sure that the phase error is by some other means by dual loop or something you make sure that the phase error will not increase beyond this range you can then limit the range of the tdc but in general number of delay cells is proportional to the reference clock period it is directly proportional and inversely proportional to the resolution of tdc which is also called as delta t lsb ok so more better the resolution more delta more the number of delay cells now you may ask that whenever you are designing any such things more number of delay cells will take more area okay so why we would like to have that well the answer lies that when you are quantizing the phase error so you had this phase error if you go back okay so here if you look at it the region where your rising edge lies is this okay so based on your logic you can say either my phase error digital equivalent is this or counta here like 9 times tlsb or you can say i will count because it is coming after this but the other edge i have not got so i will count this so your digital equivalent or you can say measured phase error has quantization error limited by let us that is a better word it is limited by mod of delta t lsp by 2. so actual if you are if you are doing it in an analog manner then whatever this phase error it is exactly this delta t ok but what you are saying is my phase error is either the value is 9 times delta t lsb which is actually less than the delta t error and if you say it is equal to 10 times delta t lsb which is more than the phase error so your actual phase error whatever you are writing 9 times t lsb if this is the value of dt dc okay if dt dc says the actual phase error delta t gets added with the quantization noise q tdc okay to give you 9 times delta t lsb so tdc comes with inherent quantization noise and this quantization noise is limited qtdc is limited between plus minus delta t lsb by 2. so you are not measuring the phase error exactly but what you are measuring is phase error within in addition to the or phase error in addition to the phase error what you get is a quantization error okay so the tdc block which is measuring the phase error between r and v signals and gives you dtdc the small signal model of this small signal model now this can be represented by you have you can write i am having a phase error as phi reference and five feedback i subtract this phase error and i multiply by the gain what is the gain of the tdc or let me just write as ktdc plus i add the quantization noise qtdc and then i get dt dc okay that is the small signal model of td c okay if you are not doing any noise analysis then we can ignore q t d c but this is what exactly happens right and k t d c we have seen it depends on what range you are implementing with how many bits so we are implementing a range of 4 pi then in that case this is 2 power n divided by 4 pi this is the k okay so this is how we will detect the phase error to give us the digital word which is used in the blue field which is used by the blue filter okay thank you