Lecture 4: Digital System Design with PLDs and FPGAs

Overview

• Review of synchronous sequential circuits.
• Focus on synchronous counters, specifically a mod 6 counter.
• Importance of timing analysis in circuit design.

Synchronous Counter Basics

• Synchronous Counter: Simplest synchronous sequential circuit.
• Mod 6 Counter: Counts 0 to 5 and back.
  • Requires 3 flip-flops (log2(6) = ~2.585, round up to 3).
  • Flip-flops are shown as a combined unit for simplicity.

Counter Design Process

• Present State: Current count represented by flip-flops (q2, q1, q0).
• Next State Logic: Determined by a combinational circuit that decodes the present state to the next state.
• Truth Table: Key for designing the combinational logic.
  • Inputs: Current states (q2, q1, q0).
  • Outputs: Next states (d2, d1, d0).

Timing Analysis

• Clock-to-output delay is essential in designing synchronous counters.
• The counter output does not change immediately with the clock edge due to delays.
• Transitory States: Occur briefly when transitioning between numbers (e.g., from 1 to 2).

Complex Counter Design: Up/Down Counter

• Up/Down Control: Modifies counting direction based on a control signal.
  • Up (1): Count up sequentially.
  • Down (0): Count down sequentially.
• Truth table expands to include the up/down control input.

Asynchronous Counter Discussion

• Asynchronous counters can be faster but have challenges due to unbalanced path delays.
• Races: Can occur due to different propagation delays in feedback loops.

Timing Parameters of Sequential Circuits

• Maximum Frequency: Determined by the delays in flip-flops and next state logic.
• Setup Time: Minimum time data must be stable before the clock edge.
• Hold Time: Minimum time data must be stable after the clock edge.
• Clock Skew: Variances in clock timing for different flip-flops can lead to hold time violations.

Design Example: 60-Second Timer

• Clock Source: High-frequency oscillator (e.g., 1 MHz) divided down for a 1-second pulse.
• Counter Design: Use of a BCD counter for the least significant digit and a mod 6 counter for the next digit.
• Display: 7-segment LED display driven by a decoder.

Design Considerations

• Power Dissipation: Higher frequency can result in increased power consumption.
• Accuracy: Higher frequency oscillators improve accuracy in timing.
• Area: Design efficiency can sometimes be improved by combining counters or reducing flip-flops.

Conclusion and Further Learning

• Importance of considering function, timing, electrical specifications in any design, whether simple or complex.
• Encourage students to think critically, ask questions, and engage in practical design experiences for deeper understanding.
• Next lecture will focus on a more complex design methodology.