So, welcome to the fourth lecture of digital system design with PLDs and FPGAs. Before continuing I will run through the previous lectures slides to be in sync. So let us move on in the last lecture we have seen the synchronous sequential circuit.
It is structure, the design and we will do the timing analysis today. But quickly we said that the synchronous counter is the simplest synchronous sequential circuit we can learn. So we try to build everything you know starting with the synchronous counter.
So suppose we have taken an example of a mod 6 counter which counts sequentially. from 0 to 5 and back to 0 and so on. So, we said that you need for binary encoding 3 flip flops because logarithm of 6 to the base 2 is 2 point something and. So, we take the integral number of flip flops as 3 and I also said that we will not show individual flip flops we will show it together because we are trying to build complex system.
So all the clocks are tied together when the reset comes this is 0 that is all we have. Now in the next clock head you have to have the 1 and the next clock head you have to have the 2. So, the idea is to decode the next count from the present count. So we put A combination circuit here before the flip flops or registers and take the present count and try to decode the next count.
So that when the clock comes the next count becomes the present count and we call it present state, state of the. counter and this is the next state which becomes the present state upon the clock. And this combinational circuit has to be designed and that we know that we have to design the truth table we have to write the truth table. So to be able to design that and we write the truth table in terms of input as q2, q1, q0, d2, d1, d0 then form 3 equations for d2, d1 and d0. So you get di as fi.
of q2, q1, q0, i is 0, 1 and 2. So, we say next state is a function of the present state and you should know that basically all the intelligence or the computation is in this combinational circuit. The flip-flop just holds it, store it for it to work at the precise edge you know when the clock comes this is let in okay that is the function of the. It serves as a memory to hold and the precise timing is achieved by the clock.
So everything is in synchronous with the clock. The state of the count change in synchronous with the clock that is why it is called synchronous counter and we said. Suppose you want to design a mode 6 counter which does not count in this sequence, the sequence may be different it is not in order but like the sequence could be 0, 5, 3, 2, 1, 4, 0 and back and that case it is simple you do not do anything you change the truth table to reflect this sequence then you get that counter.
So that is very simple. And we have looked at the output waveform, so the count changes upon the clock but not immediately there is a clock to output delay of the flip-flop and we know that there are you know this shows the multiple bit 3 bits. And there are 3 delays q4, q2, q1, q0 so we represent the worst case delay and you should also know that many a times this transition is not that it will transit smoothly from 1 to 2 because 1 is represented as 001 and 2 is represented as 010. In between there could be transitory state in this case there could be a state 3 for a brief duration here I have not shown that but.
Normally when you simulate a circuit you will be able to see that for ease of drawing I have not shown and it is very difficult to say practically whether it will happen or not it might happen sometime we will see when it happens okay. And I also reminded you last time saying that when we abstract to the next higher level do not lose sight of the detailed diagram. So, we are showing the three flip flops together everything together but you should know that these are three flip flops are separate.
The d0 is a function of in this case only q0 but in general case d0 can be a function of q2 q1 q0 again same d2 and d1 could be a function of q2 q1 q0. So, there are different circuits like you have a d0 there is one inverter which is which is one level. But when it comes to D1 you have an XOR gate which is just one level but the gate is complex and when it comes to D2 there is an AND gate and an XOR gate.
So the delay from the present state to the next state is different for different the flip flops different paths. This should be kept in mind sometime when we see a picture like this that is not evident but that you should not lose sight. of the detail that inside you should be able to view the d2, d1, d0 as separate paths with different levels and different complexity and so on.
So that is why I showed this picture so keep that in mind. So let us move on let us see the more complex counter suppose I want to design a mode 6 vector with up. and down control that means there is a control called up down when it is 1 it will when it is 0 it will down count when it is up it will up count okay. That means we have to have an up down control when it is. say 0 it will be down counting that means if it is we start with the reset 0 when the clock comes if the up down is 0 then the next state will be 5 then 4, 3, 2, 1 if it is 1 then from 0 it starts 1, 2, 3, 4. So how do we accommodate this that is the question but we know that in a synchronous counter the present state is upon the clock. the next state.
So all this has to whatever happens has to happen at the input d here that means when the clock comes this is only moved here so this up down should come in the next state logic. So, essentially we give an input to the input it is a single bit it is shown as a bus but it is just single bit. So, when it is 0 it down count when it is up it is up count.
So, essentially we change the truth table of the next state logic then you get up down counter. So, let us look at the truth table. So, now the truth table is becoming little more complex you have the present state which is q2, q1, q0.
and the input up down. Now the next state we decode as a function of the present state and the inputs okay. So you have a column for d2, column for d1 typically in manual process you will pick all the ones form the min terms minimise it and all that.
But as I said we are going to use The higher level tools which will do the minimisation, so we do not bother about the whole minimisation process we try to represent this table in some form of hardware description language. Maybe we will enumerate every case in the most simplest case or in some abstract form in a high level form we will represent this truth table very concisely. And we go to the VHDL language.
But the thing is that we get three equation now it is a function of not only the present state q2, q1, q0 it is also a function of the input. So we say in this case next state is a function of the present state and the input. So if you go back to the diagram so the next state is a function of the present state which is fed back from the flip flop and the inputs okay.
This shows that you can give you know you can give a very complex counter. Suppose one issue with this reset is that this reset is asynchronous okay. It means that as soon as you make the reset active this goes to 0. But if you remove the reset and if the clock comes immediately then this will become 1. So otherwise all the other counts starting once you start. The other counts is of the duration of one clock period okay.
So you can watch this the waveform, so the waveform shows that this count remains there for one clock period. But the 0 may not remain in the case of asynchronous reset maybe we will reset the counter here immediately the clock comes then the 0 will be there only for a short duration. So there is an issue in this case with the starting state.
the 0 state then once you started then everything is okay but the next 0 which is kind of. Coming back will be okay but the starting 0 is an issue. So if you want that to be perfect of at least 1 clock duration then you have to have a synchronous reset. So it is very simple you give a reset here and change the truth table and say that when the reset is asserted this is 0. So clearly upon next clock the 0 will come here and that will be remembered for the 1 clock period.
So you could have any kind of suppose. you want to load some value into this counter and start counting from there. Say you want to load 3 very simple then you give a load control here and an input then when the load is high you say the next state is that input thereafter if the load is low it counts depending on up and down then you get a presetable counter okay. So it is very simple you can write the truth table with the load. the reset, up down everything any complex counter can be made and if you think of it it is very easy even in terms of the high level function the reset can be thought of as a mux here when the select line of the mux is the reset line when that is asserted we give a 0 and it goes there okay things like that so or a mux here.
at the output and we can view all these in terms of various multiplexers which we will see probably later. For the time being let us assume that the combination circuit functionality is changed by the truth table. So that is what I wanted to convey. So you can have in principle various synchronous control like you can have a control called count by 2. If it is active the counter will count by q like instead of 0, 1, 2, 3 it might go 0, 2, 4, 6, 0 like that.
You can have a synchronous reset very properly it will reset and this is very important because many counting applications is used for timing the precise timing and we cannot have any ambiguity that one state is only half. So, in such cases it is better to have synchronous reset, we can have a control called skip3, if skip3 is active then 3 will be skipped and as I said you can preset some values by asserting load. Then there is an input 3 bit input which is this shows the din2, din1, din0.
So that is the meaning of this, so when the load is high this value is loaded on to the counter. So, all this can be incorporated. That you should know so you know all about how to build any counter, counter which can count in any sequence any complex operation you need not worry like you need not learn what is inside and worry about it and moreover we are designing complex system so that we can use.
hardware description language to represent all these behaviour in a little more abstract way than enumerating like in a truth table. We will see that when we learn the VHDL. So the next question I want to ask is that you we have talked about a synchronous you know sequential circuit synchronous counter can we have an asynchronous counter that means we do not have.
In this case what happens is that when the clock comes the next state come to the present state. That means if we start with 0 next clock comes the 1 comes here and that goes there and it decodes 2 and 2 is ready next clock comes. 2 comes here. But all the intelligence is in the combinational circuit, but if you see the purpose of the flip-flop is to kind of hold the value here so that this logic will work properly and secondly it is precise timing when the clock comes the things change at the exact instant okay of course with the delay. So the delay is kind of fixed.
Then at the same time at the same interval this change happens over and over. But the question is that if that is the purpose why not suppose the propagation delay of this flip flop is 1 nanosecond say. Then what we will do is that between d2 and q2, between d1 and q1, d0 and q0 we insert buffers of 1 nanosecond delay and make at the beginning make this present state 0 by asserting a signal then will it count 0, 1, 2, 3 like that.
We have no control over the timing it will go very fast as fast as the depending on the delay. But will it work? So the answer is that it will work there is no issue but you should remember there is an issue here which I have mentioned earlier the decoding circuit of D2, D1, D0 might incur different delays with respect to this point okay we might put.
1 nanosecond buffer is exactly here but when from the present state to the next state there are 3 circuits 1 for d2, 1 for d1, 1 for d0 maybe one is slower than the other that can create problem. So take this case we have a count 1 here 001 which is going to count 2 which is 0 1 0. Now what happens is that there is a change in q0 q1 and q2 does not change. Assume that the q1 is faster than q0, so what happens is that before q0 transit from 1 to 0 q1 transit from 0 to 1. So in between going from 0 to 1 to 2 there is for a brief duration. There is a state called 3 or the count called 3, now if that remains there for this propagation delay then the whole game can change the next state becomes 3 and we lose control. So the trouble with asynchronous circuit is that it is very fast when you want very high speed operation this is good but wherever there is a feedback it creates problem because there is unblocking.
unbalance path delay in the multiple path and there could be raises and we call this raise two output can raise and there could be intermediate values things can go wrong. So, that is why we use as far as possible synchronous circuit particularly when there is a feedback it is easy to design synchronous circuit than asynchronous circuit. But whenever there is no kind of feedback one can go for asynchronous circuit.
So that is summarised here yes asynchronous circuit is possible but the trouble is with unbalanced path delay there could be races in output. It is difficult to design and. control it is very fast ok.
So that is about the asynchronous counter or asynchronous sequential circuit. So let us move on to the timing part of the synchronous counter we have designed. So the question I want to ask you is that what is the maximum frequency of this counter that means we have a clock. How much frequency the maximum we can apply to this clock okay that has to be determined because above which it may not work okay. So, definitely that depends on the delays of the blocks involved the delay of the flip-flop and delay of the next state logic.
And you for a moment you think a clock edge active clock edge comes here then the present state will change after. TCO delay then that comes here it propagates through the next stage logic and comes here okay. So there is a TCO delay and TCOM delay and there are 3 paths you know D2, D1, D0. Not only 3 paths I mean 3 outputs but there could be 9 paths we will see that 9 paths but because for each d2 the input can come from q2 or q1 or q0 there are 9 paths and we have to take the maximum delay. And now you know that before the next clock edge comes data has to be stored.
steady here some time before called setup time. So we have seen that for the flip flop to work properly the data should appear here some time before the clock edge and it should remain some time after the clock edge. So the clock period should accommodate all that delays and we will see it pictorially.
So let us take this as a clock and a clock edge comes here. So Say it takes this much time the TCO time for the data to change here. So it changes there you see the present state changes there and then it propagates through this combinational logic and the data at this point the data changes here after a combinational delay. So that is what I have shown after the first clock edge the data changes at this point after the TCO delay.
And at this point after the tcom delay so the data arrives here the TCO plus tcom delay after the clock edge but we know that before the next clock edge comes the data has to be here some time before called setup time. okay. So now that means there has to be some gap at least this line and this line can touch but it cannot go before okay. So that means the total the clock period t clock should accommodate tco, tcomp and tsetup okay.
So that is what is shown here the minimum clock period minimum you can go should be greater than. TCO maximum clock to output time, Tcomp maximum like there are many paths we have to pick the maximum delay and the maximum setup time and that gives the minimum you can go. So the maximum of frequency will be less than 1 by T clock min because This is becoming this is the maximum value so the frequency maximum we are taking it in the denominator.
So, fmax should be less than 1 by t clock min but it is not good to like in this like it is not good to keep it. equal then any temperature variation if the propagation delay becomes more then there is an issue. So, we normally give a margin and that margin is called slack which is the all these three quantities subtracted from the t clock will give you a slack okay.
But the surprising thing is that in this equation the whole time does not picture at all okay does not looks like it does not matter the whole time does not matter for the maximum frequency maybe at the beginning it is little bit of a surprise. But then we have to see whether the whole time. is kind of met in this case and what is the condition that it can be violated. So let us look at this picture the whole time say when a clock edge comes okay here you say let us take this clock edge. Clock edge When the clock edge comes it says that whatever data was there before the clock edge that should remain for some time afterwards okay.
But we know that when a clock edge comes the data at this point is going to change only after TCO plus TCOM delay ok. So the whole time if TCO plus TCOM you know that the next state will change only after this propagation the clock edge comes it propagates here then it propagates here then it changes there. So it is enough if the whole time is less than TCO plus TCOM or other way TCO plus TCOM. should be greater than that whole time and mind you now we have to take the minimum TCO. In the maximum frequency case we pick the maximum delay of the TCO and TCOM to accommodate the T clock.
But in this case the minimum is the constraint because there could be a case where one of the say Q0 is very fast TCQ0 is fast. And from q0 to one of the input is very fast then there could be a problem. So we say tco min plus tcom min should be greater than the t hold max okay.
Now that looks at least pictorially it looks. kind of an impossible condition to violate and now if you pick a flip flop ok and just analyse the timing of the flip flop and if the flip flop itself the TCO is greater than of the flip-flop this cannot be violated at all the TCO min or the least TCO is always greater than the whole there is no question of this violation ok. So, looks like whole time can be violated but. In whatever in this our analysis there is something hidden which we have not stated so that is very important. So here we have assumed that the clocks for there are 3 clocks going to 3 flip flops.
But we assume that the clocks are arriving at each flip flop at the same time. So but in real life that may not happen and that is called skew the clock may be skewed. skewed with respect to each other that means the clock 2 may be coming earlier than the clock 1 and clock 0 may be arriving later than the clock 1 and so on okay. So this equations will change and there could be hold time violation when there is clock skew and the worst case can happen when there is no combinational delay like assume that for some reason the combinational delay is small or nil.
delay and you already know that we build a shift register the one flip flop output will go to the next flip flop input. So in such case there is no combinational delay and if there is a clock skew there can be hold time violation okay. So So, this is important to remember and we will analyse the case with the clocks queue.
But this is the main as far as the sequential circuit is concerned the next important thing is the maximum. Frequency of operation and the hold time violation these two things are the important timing parameter of the sequential circuit synchronous sequential circuit and mind you that is built on. simple combinational delay and the flip flop timing parameters like TCO, Tsetup and Thold. So we have very simple things the propagation delay of the combinational circuit and the propagation delay of the flip flop, the setup and hold time, the next level of the timing details are built on this the maximum frequency and the hold time violation. So that is at the next level that is the most important thing.
So quickly I have stated whatever I have told. So, these are the basic parameter and rest of all is built on that. And we assume that the clock is not skewed in this case when there is a clock skew we have to analyse it and we will analyse it later and the hold time violation okay one thing to remember suppose we build a circuit like that and we gave some clock we suppose we gave a say 500 megahertz clock here which gives say 20 nanosecond clock.
2 nanosecond clock period and if this is violated then what to solve the problem you have to kind of increase the clock period. there is a this inequality is violated to solve it is to increase the clock period. But assume that this is violated TCOmin plus TCOMmin is greater than the old time the increasing the frequency would not help at all.
all because there is no t clock period in the in this inequality. So there is no point in suppose this is violated the only way is to increase the combinational delay. So we may have to when there is a hold time violation we may have to introduce additional delay in the combinational path.
That is how to sort out the hold time violation that is what I stated here when a minimum clock period condition is violated this can be met by increasing the clock period. But when there is a hold time violation you need to increase the combination. combination delay.
Again I stated in a flip-flop TCO can be greater than the whole time and if no clock skew the whole time cannot be violated. But when there is a clock skew and when the combination delay is minimum or 0. 0 like in a shift register this hold time violation can happen then you have to introduce the additional clock delay. So let us look at the number of paths probable paths in the previous circuit. So suppose in the case of a mode 6 counter there are 3 flip flops and total number of probable register to register paths are 9. Because For from each qi to each dj there could be a path okay in the case of a very simple sequence it may not be there but in general there could be a path from like we know that the q0 is a function of sorry d0 is a function of q2 q1 q0. So when you build the circuit for that d0 there is a path from q0 there is a path from q1 q2 so three paths.
For each d0, d1 and d2 there are 9 paths. So essentially as far as the timing is concerned it is to analyse this register to register path. okay. It need not be synchronous counter like in timing analysis we look at from each register to one source register to the one destination register path need to be analysed for to find the maximum clock frequency and to find the whole time violation. So that is the basic game.
So, in general when you look at the sequential circuit there is some source register which is holding some value which is passing through a combination of circuit for some computation and it reaches the destination register and we have to make sure that this like inequalities are met. So here that there is a source register. which supply the data to a destination register through a combinational circuit. Then the clock min should be greater than tco plus tcom plus or equal to tco plus tcom plus t setup with some margin and the hold time violation to avoid then you have the tco min plus tcom min should be greater than.
the whole minimum. So this is the most general case of the timing a register to register path where in you can find the maximum clock frequency and the condition for hold time violation. So we have abstracted it from the taking.
A synchronous counter an example and come to a very general sequential circuit it need not be synchronous counter anything can be analysed in this manner. So let us move on. So let us make things little more complicated or complex.
Let us take a flip flop we know that the setup time and hold time is specified at the input that means the we know that the So, the timing parameters state that with respect to this clock there is a setup time the data has to be setup sometime before data has to be held sometime after. So we take an example of setup time being 2 nanosecond and hold time being 1 nanosecond. Then the data width the minimum width of the data is like that.
Data is changing from 0 to 1 just before the 2 nanosecond, it remains for 2 nanosecond up to the clock and one more nanosecond and it changes okay. But many a times like we may take this input at a pin on a chip like you know on an FPGA and we would like to know and that might like the wire is going from the pin through some buffers and reaches here. So there could be additional delays in the data path as well as in the clock path but for analysis we will separate this case it is easy to analyse and look.
and grasp the concept and then we can you know you can put it together. So here this point incur a delay of 2 nanosecond that means you give a data here it appear here after 2 nanosecond delay and when you supply a clock assume that the clock has no delay. We would like to know what is the setup time and hold time with respect to this point because we have control over this point we are supplying the data from outside at this point. point and we are not worried about the setup and hold time here that does not help us because there is an additional 2 nanosecond delay.
So whatever we put here appear here after 2 nanosecond. So you see this data. Here comes earlier by 2 nanosecond d dash, so I have moved the data at this point by 2 nanosecond to the left.
Now assume the clock is same. So, what is the new setup time at this point d dash now the setup time you see with respect to this clock setup time has increased because the data at this point has to be setup 4 nanosecond before. Because this 2 nanosecond plus this 2 nanosecond delay data d dash has to be setup 4 nanosecond before the actual clock.
So this 2 nanosecond is added to the setup time setup time is increased now whole time you see. Whole time is 1 nanosecond towards left ok. Now one thing to remember is that setup time is defined as the time before the clock edge the data has to be setup. So and the whole time is defined as the data has to be held after the clock edge. clock edge.
But in this case you know the data is removed before the clock edge so it becomes negative. So whatever was 2 nanosecond this delay is removed. is you know you have 1-2 you get nanosecond and do not worry about that nanosecond it essentially means that you can remove the data normally you remove the data after the clock edge when the hold become negative in the opposite direction it means that you can remove the data at this point even before the clock edge ok. So if you do that at this point correctly the data will match this window of the setup and hold time.
It essentially means whenever you have a delay in the data path or the this path then the setup time increases and the hold time decreases and the hold time can become negative you need not worry it means that the data can be removed even before the actual clock edge. So that at the input of the flip-flop everything happens very correctly. So that is the case with when there is a skew in the data path let us analyse the other case that. When there is a skew in the clock path what happens ok.
So this is summarised whatever I have told a delay in the data path will increase the setup time, decrease the whole time, minus t means data can be removed before the active clock edge, setup time is defined before the setup, before the clock edge and the whole time is defined after the clock edge. So whenever it goes in the opposite direction it is a negative value. So that what it means. So, let us take the next case where.
There is a skew in the clock path and that means we have a pin here we give the clock and that suffers a delay of 3 nanosecond before it reaching this particular flip flop. And we would like to know what is the relation of the data setup time and hold time with respect to this clock that is where we have control. So the actual clock here is shown here this is the clock and it has a setup time with respect to this point 2 nanosecond and hold time. So, in the normal case the data appear here with you know because there is a 2 nanosecond here and the clock you see here the clock dash will appear earlier to this clock by 3 nanosecond. So, that it will appear correctly here.
So, now you can see that this edge of the clock is moved left by 3 nanosecond okay. So, now at this point our timing is with respect to the new clock. or the clock dash.
Now you see the data has to be set up at this point after the active clock edge. So the setup time was 2 nanosecond but now it has become 2-3 nanosecond which is nanosecond that means data is set up at this point after the clock edge with respect to this clock point. So that is the minus but it has to be held for 1 plus 3 nanosecond become 4 nanosecond. So, the whole time is increased by 3 nanosecond by this queue. So, it means that if there is a queue in the clock path the setup time is reduced by that much and the whole time is increased and in this case setup time can become negative.
It means at that point with respect to this new clock the data is setup. the clock appears here so that at this point everything you know works correctly. So that is what is summarised here when there is a delay the setup time with the new reference point is decrease and hold time is increase. And negative setup time would mean that it can be setup after the reference clock okay. That is what about so this is what I have you know covered in the last few slides.
Basically we have looked at the structure of the synchronous sequential circuit. We have taken an example of a synchronous counter, we have looked at the main components like the flip flops, the next state logic you know which decodes the present state make the next state. So basically two components next state logic which decodes the present state and the inputs. When you give inputs you give inputs to the next state logic that it can. control the next state in a desired way like synchronous reset, load and up down and things like that any complex operation.
Only thing is that we change the truth table accordingly then you get the functionality and we also said that you know there are you should not lose sight of the detailed view because there are lot of paths within that simple diagram. which should not be lost sight and we have looked at the asynchronous circuit and we have seen there could be races because there is unbalanced path delay in the case of feedback. So it is difficult to design and control so we stick to the synchronous sequential circuit synchronous counter in that case we have looked at the timing and we have looked at the condition for the maximum frequency of operation. We have looked at the condition for the hold time violation these are the two main things which is built on the basic timing parameters. Then we have looked at the case where there is a what happens to the setup time and hold time when there is a skew in the setup path when there is a skew in the clock path.
What happens with the setup and hold time with the new reference point that is very useful in analysis if you do not grasp that many a times you cannot analyse things properly. So let us move forward let us look at how to go about designing some system digital circuit. So let us move on say take an example suppose I want to design a 60 second simple timer ok which counts.
like say 0 to 60 that is all and display it maybe for some practical purposes like we have a counter which counts little accurately from 0 to 60 in sequence. 0 to 59 mode 60 counter very precisely like every 1 second it should change. So how to go about designing that is a very simple thing let us start with a very simple design.
So how do we design such a thing ok. So let us look at the slide. So the first thing you need is a 1 second clock. But you do not get a 1 second oscillator you have to build, oscillators are high frequency oscillator you cannot have a crystal vibrating at 1 second period. So you have to have high frequency oscillators maybe 1 megahertz maybe 10 megahertz or 500 megahertz then you divide using counters to get a 1 second pulse.
The moment you have a 1 second clock you can it to a counter and start counting. So let us put that in the picture. So we have a clock oscillator which is of high frequency maybe let us assume it is a 1 megahertz clock and then we put a divider. So if you put a 1 megahertz clock you know that it has to be divided by somewhere around you know nearing around 2 raise to 20, 2 raise to 20 is a binary number more than 1 meg.
But you need at least 20 flip flops with some more to like mod 1 meg counter to divide this and here you get a 1 second pulse ok. So we will make a very simple design. So for to count from 0 to 59 we will put a counter 2 part. least significant digit will count from 0 to 9 and when it reaches 9 it will increment a mode 6 counter which is counting from 0 to 1 like that. So we will put a BCD counter which counts the least significant digit when it reaches 9 it will increment.
And a mode 6 counter which goes from 0 then when it reaches 9 it goes to 1 and so on. Now we have to display it, so we need a 7 segment some kind of display simple thing let us take a 7 segment LED. So we need a BCD to 7 segment decoder here we can still use a BCD to 7 segment decoder Then we can drive some LED to light it up okay it is very simple when you have given some simple design like this you are able to design from one end you know you start with the clock you put the divider put a counter put some.
some decoder things like that. When you are thorough with the digital design simple design like this can happen in a very from one end to other and you take a paper and do it and if you try to design this in a using a hardware description language it is very few statement maybe one state few statement for this divider few statement for this and something for this and you can connect it the output to the LEDs and it works perfectly fine you can add different control like reset and what not. So all that we have learnt you know you can incorporate many other controls in the counter if you need okay. But I talked about about at the beginning of the lecture there is function, there is timing, there is electrical spec. So let us investigate whether that does that matter here.
What is the function okay function we have designed okay. So is there any timing related issues here okay or even function like area such issues can be addressed in a simple case like this okay. So, let us So like if you look at this counters it count very low frequency like it counts kind of 1 second. So it is not a very high frequency design but you take this divider you see the clock of the divider is 1 megahertz so at least 1 megahertz.
So this divider is working at a high frequency than this counter. The flip flops here are clocked at 1 megahertz at least some flip flops are clocked at 1 megahertz depending on. on the design. So it dissipates lot of power here okay.
So that is an issue to keep in mind you know there is a little high frequency part compared with this. Secondly I said this need to be accurate how do we make sure that this 1 second counter is accurate and how to improve the accuracy. So that you should know that suppose this clock source has some drift say it goes say it is a 1 megahertz you know. clock source suppose it drifts little bit you know say some parts per million it drifts then you know that the drift is divided by this.
So, since it is drifting in the higher frequency the drift in the lower frequency is so much divider so the accuracy improves. So, it shows that if you instead of a 1 megahertz clock if you go to a 10 megahertz clock with the same drift you will get a better accuracy in terms of the accuracy of 1 second. So, it probably is worthwhile to go for a higher clock frequency then you should know that the divider size will increase. Like if you go to 100 megahertz the number of flip flops will increase and the frequency of operation will increase and the power dissipation will increase and suppose if it is a battery operated thing the higher accuracy might mean lower battery life and that you should know okay. And similarly look at the area of this say the BCD counter you know that it counts from 0 to 9. It needs 4 flip flops and mod 6 counter need 3 flip flops and that means it is 7 flip flops.
So can we reduce this number of flip flops ok. So think for a while. This design takes 7 flip flops can we reduce for the number of flip flops for the same functionality.
So the answer is yes because here we have split the counter like a mode 9 counter or a BCD counter and a mode 6 counter. There are 4 bit output here 3 bit output here. So for a while let us assume what we need is a counter which count from 0 to 59. So Assume that we are not splitting it we are putting it together okay that it counts we can put a 6 flip flops which can count up to say 64 and but we will design such that it count up to 59 then we instead of having a BCD and mode 6 counter we design a counter which is mode 60 counter that means we put 6 flip flops and redesign then we say 1 flip flop. But the complexity is that now here we had a BCD to 7 segment decoder decoding 4 to 7 like 4 to 7 decoder here it is 3 to 7 decoder.
But in that case we need a mode 62. 2 7 segment LED decoder okay that means we will have some 6 lines here which is using a combinational circuit you have to decode as 2 7 lines maybe we will we do not know the complexity of that decoder depends on the input output pattern we cannot say anything about the redundancy. So if you go for a mode 60 counter we may say one flip flop here but maybe the decoder here can become more. more complex than this separate decoder.
I do not know unless you literally try and find out you should not assume that that will be simpler than this case need not be. So one has to verify that whether that will be a simpler thing and definitely you know that here it is driving the LED suppose the LED to be very bright will take some current. So maybe this BCD to 7 segment output. pins has to give some 20 to 100 milli ampere for it to be visible at a distance.
So there is an electrical spec which needs higher current drive here. So even in a simple circuit like this there are issues of the high frequency, power dissipation, the area conflicting requirements of area we do not know. We cannot a priori say that this is a better scheme than mode 60 counter or anything like that. So So, my advice is that seeing something simple you should not assume that is very simple there are no issues.
There may be issues like the accuracy as we see area then the timing then electrical specifications and things like that. So, this we should keep in mind whatever the design is small or big there could be these issues to be. thought about and the text book may not teach you all this. It is for you to apply whatever you have learned in the basic and apply to the particular case and that comes with the experience comes with many a times working on simple projects implementing things then only you will be sensitized then only you will be quickly able to catch on this issue and solve the issue that comes with the experience comes with.
thinking in learning it is not that you learn everything you understand everything but thinking is an important thing and what you have learned in the text book you have to apply to the real life then only you can find the issues in real life and that is the true engineer is the one who finds the issues and quickly identify the problem areas and try to solve it and there is no. know one can say the systematic approach will help but many a times that alone will not help in a complex system some issue come up many a times you have to quickly To use a very oft repeated phrase you have to zoom in to the issue and sort it out and that comes sometime very quickly without like you cannot go from remembering all the issues and one by one looking at it many a times it clicks in the mind that comes with the experience that comes with. Your own deep understanding of the issues and the mind works very quickly seeing the behavior you will be able to quickly debug you know that is one issue I want to emphasize live circuit the debugging is very important that when you have a problem you should be able to quickly sort it out and debugging is not limited to the hardware it can be the software it can be a mechanical system. It can be be true with the mathematics you know you do not call debugging a theorem or debugging a proof. But essentially that is what is done you are like you are trying to suppose you have a hypothesis you are trying to prove it and you try work out something goes wrong.
So that what things go wrong should point you out what is wrong with the hypothesis or what is wrong with your approach to proving it and things like that. So I would say that that is debugging you know that is debugging the mathematics. So you can debug a mechanical system something is going wrong something is not moving properly you have to debug it. The concept the ideas the technique the thinking is same irrespective of whether it is abstract whether it is real life sometime you will be surprised to see.
very lowly technician applying their mind you can learn a lot when you see the real technician solve some problem in their domain. They experience people go in the correct sequence of assembling something, dismantling something, trying to locate the issue with the problem and sort it out this is an eye opener maybe they are experienced they are doing the things day in day out. But the engineering domain needs such approach such thinking such deep understanding experience and learning with the practical example always try to implement and try to If something goes wrong try to find out what is going wrong so that you go wrong less time.
Many times people repeat that you have to learn from mistake yes you have to learn from mistake but in your. career in your life you should make less mistake like you should learn as much as from the mistake that means once you make a something goes wrong then you should analyse it and learn it thoroughly so that is not repeated. So the next slide I will give a I will just sensitise we are going to a a bigger design okay. Really we will take a complex design and see how to you know how in a complex case the design can be done.
So I did not start the lecture just now because I will have to terminate it halfway. So the next step we have taken a very simple case and see how the digital design is done. The next step is that we will take a reasonably complex design and see. how the design methodology can be applied in terms of the function, timing, the issues involved how to go about knowing with the.
With the minimum knowledge how you can design is what I am going to cover in the next lecture. So I have covered some minimal things but these are very important things I have covered. So please go back review try to grasp in your mind you know think about it work on a paper try to understand ask questions to yourself. Like you should have the doubt write it down now this is a video lecture I have no way to interact with you but then you write down your question logically then try to answer it look for the answer probably you can contact me if you are stuck very much you can contact me in email I will try to answer.
So I wish you all the best and in the next lecture we will move with a complex case and thank you.