Pentium Microprocessor Overview

Introduction

• Advanced superscalar 32-bit microprocessor by Intel.
• Introduced in 1993 with approximately 3.1 million transistors.
• 64-bit data bus and 32-bit address bus, supports 4 GB of physical memory.
• Clock ratings range from 60 MHz to 233 MHz.

Historical Context

• Considered an advancement over 80386 and 80486 microprocessors.
• Significant modifications include cache structure, dual integer processing, and numeric co-processor.

Key Features of Pentium Processor

• Superscalar architecture.
• Separate data and instruction caches.
• Bus cycle pipelining.
• Execution tracing.
• Internal parity checking.
• Dynamic branch prediction.
• Dual processing support.
• Performance monitoring.

Superscalar Processing

• Allows parallel execution of multiple instructions in one clock cycle.
• Unlike scalar processors, which execute one instruction per cycle.
• Uses multiple execution units to achieve high throughput.

Architecture of Pentium Processor

Functional Units

• Bus Unit: Sends control signals and fetches code/data.
• Aging Unit: (Not specified in detail)
• Control Room: Controls u-pipe and v-pipe.
• Execution Unit: Contains u-pipe and v-pipe, each with separate ALUs.
• Caches: Data cache, code cache, and branch target buffer.

Operation

• Bus Unit: Handles external data fetches with a 64-bit bus.
• Prefetch Buffers: Load instructions into execution unit.
• Execution Unit: Processes integer and floating-point operations through separate pipelines.

Integer and Floating-Point Pipelines

Integer Pipeline (5 stages)

1. Instruction fetch
2. Instruction decode
3. Execution
4. Memory access
5. Write back

Floating Point Pipeline (8 stages)

1. Instruction fetch
2. Instruction decode
3. Register fetch
4. Instruction dispatch
5. Execution
6. Memory access
7. Write back
8. Register update

Branch Prediction Logic

• Improves performance by predicting outcomes of branch instructions.
• Static Prediction: Based on past behavior.
• Dynamic Prediction: Uses a branch history table (BHT).
• Speculative Execution: Executes instructions from predicted path before branch outcome is known.

Cache Organization

Hierarchical Cache Structure

• L1 Cache: On-chip, split into instruction and data caches (16 KB to 64 KB).
• L2 Cache: Off-chip, larger (256 KB to 8 MB).
• Maintains cache coherency to ensure consistent data across caches.

Cache Coherency Mechanism

• Ensures all caches have consistent data during write operations.

MESI Protocol

• Cache coherence protocol used in multiprocessor systems.
• States include:
  • Modified: Exclusive to one processor, modified data.
  • Exclusive: Exclusive, no modifications made.
  • Shared: Shared between processors, consistent data.
  • Invalid: Not valid data.

Conclusion

• Covered Pentium processor architecture, superscalar processing, cache coherency, and MESI protocol.
• Noted progression through advanced Pentium models (Pentium Pro, Pentium II, III, and IV).
• Emphasized efficiency and performance improvements in multi-processor environments.