Pentium microprocessor is one of the powerful family members of Intel's 86 microprocessor it is an advanced superscolor 32-bit microprocessor introduced in the year 1993 that contains around 3.1 million transistors it has a 64-bit data bus and a 32-bit address bus that offers 4 gigabits of physical memory space while the maximum clock rating offered is around 60 to 233 megahertz Pentium processor is also considered as an advancement of 8386 and 84086 microprocessor basically Pentium has included modifications related to Cache structure the width of the data bus numeric co-processor with faster speed along with providing dual integer processor in Pentium processor there are two catches one for caching data while another for caching information and each one is of 8K size by using a dual integer processor two instructions can be executed in each clock cycle the data bus width in Pentium is 64-bit which was 30 to bit in 80386 and the numeric co-processor exhibits quite a faster speed than that of 80486 let's see some features of Pentium processor Pentium processor has superscolor architecture separate data and instruction catches bus cycle pipelining execution tracing 64-bit data bus internal parity checking Dynamic Branch prediction dual processing support performance monitoring as Pentium processor is superscaler processor let's see what our superscaler processor a special category of microprocessors that involves a parallel approach for instruction execution called instructionable parallelism through which more than one instruction gets executed in one clock cycle is called superscaler processors unlike scalar processors that have the ability to execute maximal one instruction per clock cycle the superscaler processor uses the approach of simultaneously executing two instructions in one clock cycle the superscolor processors perform this task by sending multiple instructions to various execution units at the same time hence this provides High throughput super scalar processors are generally pipelined however pipelining is different from Super scaling in a way that superscalers allow execution of multiple instructions parallely using multiple execution units while pipelining uses a single execution unit which is divided into multiple phases in order to execute multiple instructions now let's see architecture of Pentium processor the various functional units are as follows bus unit aging unit control wrong refetch buffer execution unit width to integer Pipeline u-pipe and v-pipe code cache data cache instruction decode Branch Target buffer dual processing logic Advanced programmable interrupt controller let us now understand how the architectural operation takes place the bus unit sends control signals and fetches code and data from external memory and I O devices with a 64-bit external data bus the paging unit provides optional extensions for 2 to 4 megabits page sizes code cache Branch Target buffer and prefect buffers work together to load instructions into the execution unit the processor has pairs of prefetch buffers that operate with the branch Target buffer to fetch instructions sequentially until a branch occurs if a branch occurs the other prefetch buffer in the pair is enabled and starts fetching instructions from the branch Target address the execution unit contains u-pipe and v-pipe each with its separate ALU and 5 operating stages the control room provides microcode that directly controls u-pipe and v-pipe the data and code cache are organized in a two-way Associated set cache with 128 sets and two lines of 32 bytes each the code cache forms a connection with the prefix buffer through a 256-bit bus allowing 32 bytes of upcode to be buffered in one clock cycle the on-chip advanced programmable interrupt controller manages interrupt and offers 8 to 5 9 a compatibility Intel released multiple Advanced processors after Pentium including Pentium Pro Pentium 2 Pentium 3 and Pentium 4 processors integer and floating Point pipeline representation in Pentium processor the Pentium processor is a microprocessor chip manufactured by Intel Corporation it has two main pipelines one for integer operations and one for floating Point operations the integer pipeline is responsible for executing instructions related to integer arithmetic and logical operations such as addition subtraction multiplication and comparison the pipeline consists of five stages instruction fetch this stage fetches the instruction from memory instruction decode this stage decodes the instruction and identifies the necessary operands execution this stage performs the arithmetic or logical operation memory access this stage accesses memory to retrieve or store data write back this stage writes the result of the operation back to the register file the floating Point Pipeline on the other hand is responsible for executing instructions related to floating Point arithmetic and logical operations such as addition subtraction multiplication and division the pipeline consists of eight stages instruction fetch instruction decode register fetch this stage fetches the operands from the register file instruction dispatch this stage prepares the instruction for execution execution memory access right back register update this stage updates the status of the floating Point Unit both pipelines operate simultaneously and independently allowing for parallel execution of integer and floating Point instructions this improves the overall performance and efficiency of the processor Branch prediction logic in Pentium processor Branch prediction is a feature in the Pentium processor that improves the performance of the processor by predicting the outcome of a branch instruction before it is actually executed Branch instructions are instructions that determine which path of execution to follow based on a condition such as an if else statement or a look the Pentium processor uses a combination of to Branch prediction techniques static and dynamic prediction static prediction involves predicting the outcome of a branch instruction based on the past behavior of the program the processor analyzes the code and determines the most likely outcome of the branch instruction based on the instructions that precede it this is useful when the program follows a predictable pattern such as a loop or a conditional statement that is always true or always false Dynamic prediction on the other hand involves predicting the outcome of a branch instruction based on the current state of the program the processor maintains a history of the outcomes of Branch instructions in a table called the branch history table BHT when a branch instruction is encountered the processor uses the branch history table to predict the most likely outcome of the branch based on the previous outcomes of similar branches the branch history table is updated each time a branch instruction is executed allowing the processor to adapt to changes in the program Behavior the Pentium processor also uses a technique called speculative execution where the processor begins executing instructions from the predicted path before the outcome of the branch instruction is known if the prediction is correct the processor has already executed some instructions from the correct path resulting in improved performance if the prediction is incorrect the processor discards the executed instructions and begins executing instructions from the correct path overall Branch prediction improves the performance of the Pentium processor by reducing the number of pipeline stalls that occur due to Branch instructions by predicting the outcome of Branch instructions the processor can continue executing instructions from the correct path resulting in faster and more efficient execution of programs cash organization in Pentium processor the Pentium processor has hierarchical cache organization consisting of two levels of cash the L1 cache and the L2 cache L1 cache the L1 cache is located on the processor chip itself and is split into two separate caches the instruction cache and the data cache the instruction cache stores frequently accessed instructions while the data cache stores frequently accessed data the size of the L1 cache is relatively small typically ranging from 16 kilobytes to 64 kilobytes but its proximity to the processor allows for faster access times L to Cache the L to Cache is located on a separate chip but is still located close to the processor the size of the L to Cache is larger than that of the L1 cache typically ranging from 256 kilobytes to 8 megabytes the L2 cache is used to store data and instructions that are not frequently accessed and cannot fit in the L1 cache cache coherency the Pentium processor also has a mechanism for maintaining cache coherency which ensures that all catches have consistent data when a write operation is performed on a particular memory location the processor ensures that the updated data is propagated to all other caches that have a copy of the same data the cache organization in the Pentium processor improves performance by reducing the time required to fetch data and instructions from memory when data or instructions are frequently accessed they can be stored in the cache allowing the processor to access them more quickly the hierarchical organization of the cache also ensures that frequently accessed data is stored in the faster and smaller L1 cache while less frequently accessed data is stored in the larger but slower L2 cache the mechanism for maintaining cash coherency ensures that all catches have the most up-to-date data preventing inconsistencies and errors that can occur when different catches have different copies of the same data now let's see about Mesi protocol the NSI protocol is a cache coherence protocol used in the Pentium processor to ensure that all catches in a multiprocessor system have consistent data nesi stands for modified exclusive shared and invalid each cache line in the Cache can be in one of these four states modified the cache line is exclusive to One processor and the processor has modified the data the modified data has not yet been written back to memory exclusive the cache line is exclusive to One processor and the data has not been modified the data in this cache line is consistent with the data in memory shared the cache line is shared between multiple processors and the data has not been modified the data in this cache line is consistent with the data in memory invalid the cache line is not valid meaning it does not contain valid data when a processor requests data from memory it first checks its own cache to see if the data is already present if the cache line is in the shared State the processor can simply read the data from the cache if the cache line is in the exclusive State the processor can also read the data from the cache but it must first change the state to Shared to allow other processors to access the same data if the cache line is in the modified State means that the processor has modified the data the processor must first write the modified data back to memory and then change the state to shared this ensures that other processors have access to the most up-to-date data if the cache line is in the invalid State means that it does not contain valid data the processor must request the data from memory and change the state to exclusive overall the nesi protocol ensures that all caches in a multiprocessor system have consistent data by maintaining the state of each cache line in each cache when a processor modifies data it ensures that the data is written back to memory and that other processors have access to the most up-to-date data this improves the performance and reliability of the multiprocessor system congratulations on completing the Pentium processor lesson in just 15 minutes we covered a lot of ground including the processors architecture super scholar processing pentium's unique features cache coherency L1 and L2 catches and the NSI protocol we hope you found this video informative and engaging thank you for watching